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* Merge branch 'master' into nextJosh Blum2012-03-268-126/+169
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| * Merge branch 'maint'Josh Blum2012-03-262-4/+25
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| | * dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHzJosh Blum2012-03-261-1/+8
| | | | | | | | | | | | | | | This fixes the lockup/clocking condition when the following hw combo is used: USRP1 r4.5 + DBSRX + another i2c board
| | * usrp2: possible fix for invalid broadcast repliesJosh Blum2012-03-261-3/+17
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| * | Merge branch 'maint'Josh Blum2012-03-264-85/+92
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| | * Merge branch 'fpga_maint' into maintJosh Blum2012-03-264-85/+92
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| | | * B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
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| | | * fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
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| | | * b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
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| | | * b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
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| | | * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
| * | | fx2: simplify i2c code and overload eeprom read/writeJosh Blum2012-03-261-15/+24
| | | | | | | | | | | | | | | | | | | | Overload eeprom routines to do it in 1 transaction, since default will split it up into many for each byte.
| * | | Merge branch 'maint'Josh Blum2012-03-261-22/+28
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| | * | uhd: use release mode and git count for stable and unstable buildsJosh Blum2012-03-261-22/+28
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* | | | Merge branch 'master' into nextJosh Blum2012-03-231-1/+1
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| * | | Merge branch 'maint'Josh Blum2012-03-231-1/+1
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| | * | Changes preinst.in to 'echo' instead of 'ls'Nicholas Corgan2012-03-231-1/+1
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* | | | uhd: updated sync docs for timed commandsJosh Blum2012-03-231-1/+34
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* | | | Merge branch 'fpga_next' into nextJosh Blum2012-03-2312-426/+1454
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| * | | | spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
| * | | | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
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| * | | | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
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| * | | | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
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| * | | | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
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| * | | | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
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| * | | | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
| * | | | spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
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| * | | | fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
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| * | | | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-163-92/+122
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| * | | | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-163-10/+17
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| * | | | fifo ctrl: added time compare for timed commandsJosh Blum2012-03-161-3/+7
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| * | | | srb: created command queue, in and out state machinesJosh Blum2012-03-163-99/+162
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| * | | | usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-161-40/+107
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| * | | | usrp2: first pass implementation of fifo controlJosh Blum2012-03-166-10/+594
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* | | | Merge branch 'master' into nextJosh Blum2012-03-231-3/+4
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| * | | Merge branch 'maint'Josh Blum2012-03-231-3/+4
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| | * | usrp: fix for rx_frontend_core_200 dc offsetJosh Blum2012-03-231-3/+4
| | | | | | | | | | | | | | | | | | | | Mask off upper bits when setting a constant offset (I and Q regs). The sign bits (if negative) can flow off into the flags field.
* | | | sbx: various fixes and tweaks for lockingJosh Blum2012-03-231-4/+3
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* | | | sbx: mods for PLL sync resetJosh Blum2012-03-231-3/+6
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* | | | sbx: no readback during tuning, cache lock detect status when readJosh Blum2012-03-234-12/+26
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* | | | fifo ctrl: code reorganization and integer wrap-around arithmeticJosh Blum2012-03-231-65/+90
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* | | | fifo ctrl: implement timed command feature detectionJosh Blum2012-03-232-2/+12
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* | | | uhd: added setup sleep to tx waveformsJosh Blum2012-03-231-1/+4
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* | | | fifo ctrl: use regular iface for U2_REG_MISC_CTRL_CLOCKJosh Blum2012-03-232-6/+136
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* | | | fifo ctrl: various tweaksJosh Blum2012-03-234-12/+14
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* | | | fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no blinkieJosh Blum2012-03-233-1/+14
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* | | | fifo ctrl: spi core work and host implementationJosh Blum2012-03-239-38/+99
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* | | | spi: work on fw support for simple spi coreJosh Blum2012-03-2311-139/+74
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* | | | usrp2: permanent timeout increase for timed commandsJosh Blum2012-03-231-2/+6
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* | | | usrp2: implementation of timed commands workingJosh Blum2012-03-234-7/+49
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