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| | * | | barebones udp support. Compiles, but untested.Matt Ettus2009-12-219-18/+538
| | * | | 19-bit fifo handling for receive side of eth/udp systemMatt Ettus2009-12-212-45/+83
| | * | | 19 bit wide interface in prep for connection to UDP/IP state machines.Matt Ettus2009-12-215-0/+21717
| * | | | cleaned up the main ibs state machineMatt Ettus2009-12-141-9/+22
| * | | | dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ...Matt Ettus2009-12-143-10/+9
| * | | | changed debug pins to see incoming dataMatt Ettus2009-12-121-3/+4
| * | | | reorder the memory mapMatt Ettus2009-12-112-2/+2
| * | | | put new setting reg into the address space in the right placeMatt Ettus2009-12-111-1/+1
| * | | | only pull from input fifo when really consuming or pushing into the next fifoMatt Ettus2009-12-111-1/+1
| * | | | Add ability to clear state out when there is an underrunMatt Ettus2009-12-111-1/+6
| * | | | fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-113-14/+35
| * | | | ignore save filesMatt Ettus2009-12-091-0/+1
| * | | | First cut at vita tx, whole thing compilesMatt Ettus2009-12-093-27/+37
| * | | | flag packets which arrive way too early so the device doesn't sit there forever.Matt Ettus2009-12-091-2/+4
| * | | | very basic packet sending worksMatt Ettus2009-12-092-140/+50
| * | | | seems to correctly deframe packets. now need to consume them.Matt Ettus2009-12-081-12/+23
| * | | | progress on vita_tx. it compiles now, need to work on vita_tx_control.Matt Ettus2009-12-083-239/+182
| * | | | make the testbench work in this environment, without the crossclock settings busMatt Ettus2009-12-083-5/+8
| * | | | be a little more PC about itMatt Ettus2009-11-181-5/+9
| * | | | mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
| * | | | forgot to declare wiresMatt Ettus2009-11-061-0/+4
| * | | | moved regs around for vita49Matt Ettus2009-11-052-12/+13
| * | | | vita rx instead of rx_control. Ready for firmware testing. Misses timing by...Matt Ettus2009-11-054-4/+48
| * | | | put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-053-8/+17
| * | | | VITA49 rx (and tx skeleton) copied over from quad radioMatt Ettus2009-11-057-0/+1026
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* | | | connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
* | | | debug pinsMatt Ettus2010-02-251-2/+3
* | | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
* | | | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
* | | | gpmc debug pinsMatt Ettus2010-02-252-4/+14
* | | | point to the new filesMatt Ettus2010-02-251-0/+2
* | | | fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
* | | | loopback and testMatt Ettus2010-02-252-7/+38
* | | | corrected logicMatt Ettus2010-02-251-17/+7
* | | | edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
* | | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
* | | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
* | | | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-256-25/+165
* | | | Merge branch 'master' into u1eMatt Ettus2010-02-232-1/+3
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| * | | proper initialization of the ramMatt Ettus2010-02-232-1/+2
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| * | ignore emacs cruftMatt Ettus2010-02-081-0/+2
* | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-233-6/+63
* | | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
* | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-223-3/+68
* | | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
* | | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
* | | GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
* | | added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
* | | Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
* | | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
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