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| * | | | | | | | | | | | | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
| * | | | | | | | | | | | | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
| * | | | | | | | | | | | | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
| * | | | | | | | | | | | | | Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
| * | | | | | | | | | | | | | Register outputs to omap to prevent runt pulses from falsely triggering inter...Matt Ettus2010-04-233-7/+20
| * | | | | | | | | | | | | | find time_64bitMatt Ettus2010-04-201-0/+1
| * | | | | | | | | | | | | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
| * | | | | | | | | | | | | | access frame length regs from wishboneMatt Ettus2010-04-152-10/+18
| * | | | | | | | | | | | | | async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-155-37/+72
| * | | | | | | | | | | | | | async gpmc progressMatt Ettus2010-04-154-18/+173
| * | | | | | | | | | | | | | change time parameters because Xilinx IP has a 1ps timescaleMatt Ettus2010-04-151-14/+27
| * | | | | | | | | | | | | | add bus error reportingMatt Ettus2010-04-151-3/+9
| * | | | | | | | | | | | | | correct name of moduleMatt Ettus2010-04-151-2/+2
| * | | | | | | | | | | | | | progress on synchronous gpmc, but it may not be possible due to the limited n...Matt Ettus2010-04-153-43/+45
| * | | | | | | | | | | | | | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-153-3/+100
| * | | | | | | | | | | | | | handle all tri-state in the top level of gpmcMatt Ettus2010-04-153-6/+8
| * | | | | | | | | | | | | | more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
| * | | | | | | | | | | | | | more progress on synchronous interfaceMatt Ettus2010-04-144-26/+95
| * | | | | | | | | | | | | | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-142-3/+3
| * | | | | | | | | | | | | | make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
| * | | | | | | | | | | | | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
| * | | | | | | | | | | | | | probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
| * | | | | | | | | | | | | | minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
| * | | | | | | | | | | | | | lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
| * | | | | | | | | | | | | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
| * | | | | | | | | | | | | | split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
| * | | | | | | | | | | | | | added 16-bit wide atr controllerMatt Ettus2010-04-015-47/+117
| * | | | | | | | | | | | | | 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
| * | | | | | | | | | | | | | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
| * | | | | | | | | | | | | | remove timescale junkMatt Ettus2010-03-265-21/+19
| * | | | | | | | | | | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
| * | | | | | | | | | | | | | Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
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| * | | | | | | | | | | | | | | connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
| * | | | | | | | | | | | | | | debug pinsMatt Ettus2010-02-251-2/+3
| * | | | | | | | | | | | | | | enable was on the wrong address pin, needs to be the highest order oneMatt Ettus2010-02-251-2/+2
| * | | | | | | | | | | | | | | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
| * | | | | | | | | | | | | | | gpmc debug pinsMatt Ettus2010-02-252-4/+14
| * | | | | | | | | | | | | | | point to the new filesMatt Ettus2010-02-251-0/+2
| * | | | | | | | | | | | | | | fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
| * | | | | | | | | | | | | | | loopback and testMatt Ettus2010-02-252-7/+38
| * | | | | | | | | | | | | | | corrected logicMatt Ettus2010-02-251-17/+7
| * | | | | | | | | | | | | | | edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
| * | | | | | | | | | | | | | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
| * | | | | | | | | | | | | | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
| * | | | | | | | | | | | | | | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-256-25/+165
| * | | | | | | | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-02-232-1/+3
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| * | | | | | | | | | | | | | | | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-233-6/+63
| * | | | | | | | | | | | | | | | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
| * | | | | | | | | | | | | | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-223-3/+68
| * | | | | | | | | | | | | | | | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
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