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* Merge branch 'maint'Josh Blum2012-05-102-7/+9
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| * e100: bump compat minor for xclock reader fixJosh Blum2012-05-101-1/+1
| * fpga: xclock fix for edge case conditionJosh Blum2012-05-081-6/+8
* | e100/b100: bumped compat number for timed commands mergeJosh Blum2012-04-252-2/+2
* | slave_fifo: use 2KB FIFO size instead of 1KBNick Foster2012-04-241-1/+1
* | b100: implement packet-end/flush cycle timeoutJosh Blum2012-04-243-12/+26
* | gpif: removed unused gpif related filesJosh Blum2012-04-248-908/+1
* | N2x0: updated the bootloader w/ latest from fwJosh Blum2012-04-201-390/+390
* | usrp2: remove settings_fifo_ctrl, meets timingJosh Blum2012-04-201-2/+11
* | fifo ctrl: Nseries timing meets with a single shortfifoJosh Blum2012-04-171-3/+2
* | usrp: work on meeting timing constraintsJosh Blum2012-04-105-25/+30
* | Merge branch 'master' into nextJosh Blum2012-04-095-7/+67
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| * | Merge branch 'maint'Josh Blum2012-04-095-6/+6
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| | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-095-6/+6
| * | Merge branch 'maint'Josh Blum2012-04-022-5/+5
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| | * b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-012-5/+5
| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
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* | Merge branch 'master' into nextJosh Blum2012-03-264-85/+92
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| * B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
| * fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
| * b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
| * b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
* | spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
* | spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
* | fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
* | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-163-92/+122
* | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-163-10/+17
* | fifo ctrl: added time compare for timed commandsJosh Blum2012-03-161-3/+7
* | srb: created command queue, in and out state machinesJosh Blum2012-03-163-99/+162
* | usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-161-40/+107
* | usrp2: first pass implementation of fifo controlJosh Blum2012-03-166-10/+594
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* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
* dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
* dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
* dsp rework: pass enables into glue, update power trig, parameterize, fix modu...Josh Blum2012-02-109-103/+145
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
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