| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cmake: got rid of remaining references of UHD_RELEASE_MODE being treated as ↵ | Nicholas Corgan | 2012-07-02 | 1 | -0/+3 |
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| * | usrp1: revert calculation for DAC freq outside of 1st Nyquist | Josh Blum | 2012-06-28 | 1 | -36/+2 |
| | | | | | This patch does not work. A possibile solution will be added to master. | ||||
| * | xcvr2450: fix to disable LO offset for TX side | Josh Blum | 2012-06-18 | 1 | -1/+1 |
| | | | | | | | | | | | XCVR2450 has a common LO for RX and TX. The use LO offset should be the same for both sides. When different, a tune for one side will override the other side, because the DSP will not know the compensation factor after the other side is tuned. Setting both use_lo_offset to false is how this was pre 3.4 release. | ||||
| * | n2x0: fix for net_burner, continue on error | Josh Blum | 2012-06-08 | 1 | -1/+1 |
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| * | usrp1: shutoff DAC digital w/ TX state machine | Josh Blum | 2012-05-30 | 1 | -1/+6 |
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| * | examples: fix tx bursts so we only set EOB at the end | Josh Blum | 2012-05-30 | 1 | -9/+5 |
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| * | uhd: bumped patch version number to 3.4.2release_003_004_002 | Josh Blum | 2012-05-22 | 1 | -1/+1 |
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| * | Merge branch 'fpga_maint' into maint | Josh Blum | 2012-05-22 | 1 | -1/+38 |
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| | * | Added registers for gpmc-to-fifo interface to address sequence errors for ↵ | Al Fayez | 2012-05-22 | 1 | -1/+38 |
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| * | | b100: fix for 61.44 MHz clock mod docs | Josh Blum | 2012-05-21 | 1 | -6/+6 |
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| * | | usrp1: removed print from codec_ctrl last commit | Josh Blum | 2012-05-17 | 1 | -1/+1 |
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| * | | Fixing USRP1 aliasing logic | Nicholas Corgan | 2012-05-17 | 1 | -2/+36 |
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| * | | docs: removed unsupported gps_gpgsa from docs as well | Josh Blum | 2012-05-16 | 1 | -1/+1 |
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| * | | Removed GPGSA from GPS driver since Firefly doesn't actually support it. | Nick Foster | 2012-05-16 | 1 | -5/+1 |
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| * | | b100: fix use of boost cstdint here | Josh Blum | 2012-05-16 | 1 | -1/+1 |
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| * | | Throwing here causes difficulty initializing new USRPs | Jason Abele | 2012-05-14 | 1 | -1/+1 |
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| * | | usrp1: ensure frontend specs are init'd to something | Josh Blum | 2012-05-11 | 1 | -0/+2 |
| | | | | | | | | | | | This helps the case of 4x DDC no DUC for example, that way at least something empty is set to the property. | ||||
| * | | Merge branch 'fpga_maint' into maint | Josh Blum | 2012-05-10 | 2 | -7/+9 |
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| | * | e100: bump compat minor for xclock reader fix | Josh Blum | 2012-05-10 | 1 | -1/+1 |
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| | * | fpga: xclock fix for edge case condition | Josh Blum | 2012-05-08 | 1 | -6/+8 |
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| * | | n2xx: fix possible attribute error in netburner win_get_interfaces | Josh Blum | 2012-05-09 | 1 | -3/+3 |
| | | | | | | | | | | | | | It is possible on some machines (at least one in this case), for adNode to not have the attribute next. Unexplained... This may be a fix, and if not, should be harmless. | ||||
| * | | convert: fixed sc8 convert issue w/ undefined behaviour | Josh Blum | 2012-05-08 | 1 | -16/+24 |
| | | | | | | | | | | | | | | | Its important to use a signed cast when converting float to int. Then assign that signed int to an unsigned type of the same width. Its undefined behaviour when converting a negative float to an unsigned int. | ||||
| * | | usrp2: fix ad9510 register map typos | Josh Blum | 2012-04-24 | 1 | -13/+13 |
| | | | | | | | | | | | | | These register addresses should be in hex. Fortunately, they are not set in the code, so the typo did not break anything in UHD. | ||||
| * | | uhd: fix missing API export for tasks.hpp | Josh Blum | 2012-04-23 | 1 | -2/+2 |
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| * | | usrp2: removed errors='ignore' for burners for py26 | Josh Blum | 2012-04-22 | 2 | -2/+2 |
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| * | | master: Fixing comments that say SPI is LSB. | Ben Hilburn | 2012-04-18 | 1 | -2/+2 |
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| * | | n2x0: card burner fixes for python3.0 and IPv6 | Josh Blum | 2012-04-18 | 1 | -3/+5 |
| | | | | | | | | | | | | | has_key is not in python3.0, use key in dict put try catch around interface enumeration, might be an ipv6 issue | ||||
| * | | usb: do not release recv buffer in wrapper | Josh Blum | 2012-04-17 | 1 | -3/+2 |
| | | | | | | | | | | | | | | | The actual recv buffer will be automatically released when dereferenced. By releasing this buffer early we allowed for a race condition: Subsequent wrapper buffers that shared the same actual buffer could get their memory filled by new recvd packets from the USB layer. | ||||
| * | | recv: only inspect tsf on timestamp error check | Josh Blum | 2012-04-17 | 1 | -1/+1 |
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| * | | convert: give SIMD conversions prio over table | Josh Blum | 2012-04-16 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | given performance benchmarks involving the converter, when the driver is also doing other things sc8 conversions will still involve tables since no SIMD implementations exist yet | ||||
| * | | cmake: UHDVersion.cmake gets rid of git commit number if 'release' is ↵ | Nicholas Corgan | 2012-04-13 | 1 | -1/+5 |
| | | | | | | | | | specified in UHD_RELEASE_MODE | ||||
| * | | utils: card/net burner string decode | Josh Blum | 2012-04-12 | 2 | -2/+2 |
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| * | | uhd: bumped version num to 3.4.1 for releaserelease_003_004_001 | Josh Blum | 2012-04-10 | 1 | -1/+1 |
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| * | | Merge branch 'fpga_maint' into maint | Josh Blum | 2012-04-09 | 5 | -6/+6 |
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| | * | vita: moved clear register to overlap with nchan register | Josh Blum | 2012-04-09 | 5 | -6/+6 |
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2. | ||||
| * | | dsp: clear register now overlaps with numchan register. | Josh Blum | 2012-04-09 | 1 | -4/+2 |
| | | | | | | | | | This fixes the bug of unwanted clearing when setting format. | ||||
| * | | usrp: fix set_clock_config typo for external and mimo clock ref | Josh Blum | 2012-04-06 | 1 | -2/+2 |
| | | | | | | | | | | | | | This is a typo in the set_clock_config implementation. However, the enum values are the same, so this would not cause a bug. Fixed although set_clock_config is a deprecated interface. | ||||
| * | | Merge branch 'fpga_maint' into maint | Josh Blum | 2012-04-02 | 2 | -5/+5 |
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| | * | b100: fix slave fifo data xfer exit condition | Josh Blum | 2012-04-01 | 2 | -5/+5 |
| | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change. | ||||
| * | | examples: fix bsd compilation for network relay example | Josh Blum | 2012-04-01 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | Fixes compilation on platforms that dont have one of the OS defines by providing #else case for rx_dsp_buff_size constant. This also makes OSX the special case and assumes other OS can handle the large RX socket buffer size. | ||||
| * | | usrp1: stop threads in deconstructor | Josh Blum | 2012-03-29 | 3 | -4/+10 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its important to stop the threads before we let the other smart point objects naturally deconstruct to avoid thread-based race conditions. The attempt to deconstruct the tree and soft time ctrl had a bug because the tree had references in subtrees within the dboard manager class. Rather than continue to fix this method and deconstruct the tree to free up soft time ctrl, it seems simpler to just stop the thread in soft time ctrl, and then let it naturally deconstruct later by ref count. | ||||
| * | | cmake: Binaries give notification before installing or uninstalling UHD. ↵ | Nicholas Corgan | 2012-03-29 | 4 | -1/+5 |
| | | | | | | | | | Better to give an output than just an empty pause. | ||||
| * | | dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHz | Josh Blum | 2012-03-26 | 1 | -1/+8 |
| | | | | | | | | | | | This fixes the lockup/clocking condition when the following hw combo is used: USRP1 r4.5 + DBSRX + another i2c board | ||||
| * | | usrp2: possible fix for invalid broadcast replies | Josh Blum | 2012-03-26 | 1 | -3/+17 |
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| * | | Merge branch 'fpga_maint' into maint | Josh Blum | 2012-03-26 | 4 | -85/+92 |
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| | * | B100: port cleanups from b100-txbug to this branch | Nick Foster | 2012-03-26 | 2 | -28/+21 |
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| | * | fpga: fifo_2clock handles widths and sizes in-between corgens | Josh Blum | 2012-03-25 | 1 | -21/+23 |
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| | * | b100: cleanup redundant logic for slwr and slrd | Josh Blum | 2012-03-25 | 1 | -2/+2 |
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| | * | b100: extra data pktend cycle for fifo addr | Josh Blum | 2012-03-25 | 1 | -2/+8 |
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| | * | b100: slave fifo fix for dst/src ready signals | Josh Blum | 2012-03-24 | 2 | -35/+41 |
| | | | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully. | ||||
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