summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'flow_ctrl_with_fpga'Josh Blum2010-10-1577-405/+11159
|\
| * Merge branch 'flow_control' into flow_ctrlJosh Blum2010-10-1457-256/+10817
| |\
| | * now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-10-121-6/+16
| | |
| | * don't clear out following packets on an eob ackMatt Ettus2010-10-121-1/+1
| | |
| | * don't flag an error on eob ackMatt Ettus2010-10-121-1/+1
| | |
| | * proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-10-121-1/+8
| | |
| | * cleanup for 32 bit seqnumMatt Ettus2010-10-111-4/+3
| | |
| | * increase compatibility number for flow controlMatt Ettus2010-10-111-1/+1
| | |
| | * switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-10-113-14/+16
| | |
| | * send message on eob to ack the end of transmissionMatt Ettus2010-10-111-1/+6
| | |
| | * typo which isn't caught by xilinxMatt Ettus2010-10-111-1/+1
| | |
| | * separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-10-104-25/+43
| | | | | | | | | | | | without flow control
| | * go to the correct stateMatt Ettus2010-10-081-3/+3
| | |
| | * add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
| | |
| | * add trigger to makefileMatt Ettus2010-10-081-0/+1
| | |
| | * assign setting reg addressesMatt Ettus2010-10-081-2/+2
| | |
| | * declarationsMatt Ettus2010-10-081-2/+3
| | |
| | * checkpoint in flow control packet generationMatt Ettus2010-10-085-42/+147
| | |
| | * revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
| | |
| | * reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
| | |
| | * Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | * ise12: fix timing problem on DAC output bus clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
| | | * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| | | |
| | * | Modified phase shift of DCM1 to -64 which is intended to give more timing ↵Ian Buckley2010-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
| | * | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵Ian Buckley2010-09-141-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
| | * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-09-014-5/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
| | * | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ↵Ian Buckley2010-09-015-47/+60
| | |\ \ | | | | | | | | | | | | | | | efifo_merge
| | | * | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
| | | | |
| | | * | Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-08-255-46/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
| | * | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
| | |/ /
| | * | capacity logic fixMatt Ettus2010-08-191-1/+1
| | | |
| | * | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
| | | |
| | * | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
| | | |
| | * | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_efifo_work: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Conflicts: usrp2/vrt/vita_tx_deframer.v
| | | * | Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-08-199-238/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
| | * | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * features: added compat number to usrp2 readback mux makefile dependency fix for second expansion
| | * \ \ \ Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'tx_policy' into ise12_efifo_work * tx_policy: rx error context packets should not be marked as errors in the fifo provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host checkpoint. New context packet generator to report underruns and other errors Conflicts: usrp2/top/u2_rev3/u2_core_udp.v
| | * \ \ \ \ Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-1610-33/+180
| | |\ \ \ \ \ | | | |_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet fix to stop endless error packets updated tests to match new features error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets reload bit for vita rx ctrl
| | * | | | | Regenerated FIFO's for extfifo.Ian Buckley2010-08-1212-728/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are problems with certain configurations it seems. It is important that the fifo_xlnx_512x36_2clk_18to36 is generated with the "almost_full" pin even though it is not used in the application. if this pin is omitted the FPGA image doesn't work correctly
| | * | | | | Edited FIFO instance to delete port that was not regenerated after ↵Ian Buckley2010-08-121-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | reconfiguration
| | * | | | | Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-08-125-0/+808
| | | | | | |
| | * | | | | Bringing all coregen files checked in into syncIan Buckley2010-08-1210-137/+60
| | | | | | |
| | * | | | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv ↵Ian Buckley2010-08-1218-41/+587
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into ise12_efifo_work Conflicts: usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc Resolving conflicts by regenerating files clenly in ISE12.1 coregen
| | | * | | | | checkin of generated coregen filesMatt Ettus2010-08-1118-8/+556
| | | | | | | |
| | * | | | | | Found bug due to not accounting for the correct number of possible in flight ↵Ian Buckley2010-08-127-49/+113
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus
| | * | | | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-07-3119-238/+7327
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
| | * | | | | Checkpoint checkin.Ian Buckley2010-07-2913-0/+1507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet.
| | * | | | | get it to buildMatt Ettus2010-07-145-5/+309
| | | | | | |
| | * | | | | moved forward from the old branchMatt Ettus2010-07-148-4/+876
| | | | | | |
| * | | | | | uhd: removed 1 sample buffers in test async messagesJosh Blum2010-10-142-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | made a hack in the vrt handler to bump 0 sample requests up to 1 sample (until the hardware supports it)
| * | | | | | usrp2: move udp port initialization into mboard impl so its done before ↵Josh Blum2010-10-144-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | async registers are setup
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 21:32:16 +0000