summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* usrp2: bump FPGA minor number to 2 for patch releaseJosh Blum2011-08-152-2/+2
* connect unused BRAM inputs to 1s to save routing logicJosh Blum2011-08-151-1/+1
* dsp: clear cic_decim when not enabledMatt Ettus2011-08-151-4/+4
* N2x0: print constraints summary from makefileJosh Blum2011-08-151-0/+1
* N2x0: added a Makefile to build all N2x0 projects (make -j4)Josh Blum2011-08-151-0/+22
* N2x0: delay ADC A inversion so A and B are latched in the sameJosh Blum2011-08-151-3/+5
* B100/E100: fix ATR RX mode pins not connectedNick Foster2011-08-102-4/+4
* time: register time output to help fpga timingMatt Ettus2011-07-281-2/+5
* vrt: delay the late signal to help with timingMatt Ettus2011-07-281-5/+20
* dsp: allow tx iq balance to be removed at compile timeMatt Ettus2011-07-281-23/+38
* dsp: option to remove iq compensation at compile timeMatt Ettus2011-07-281-35/+40
* time64: reverted mimo sync changes to time64Josh Blum2011-07-281-3/+1
* u2/u2p: speed up time_64, and remove readbacks on simple_gemac wb regsMatt Ettus2011-07-282-11/+13
* simple_gemac: remove old 19-bit wide wrapperMatt Ettus2011-07-284-402/+0
* usrp2: remove old unused readback mux valueJosh Blum2011-07-282-2/+2
* usrp2: bump minor version number for changesJosh Blum2011-07-282-2/+2
* vita_rx_ctrl: use an extra cmd bit to signal stopJosh Blum2011-07-281-7/+7
* usrp2: fixed swapped tx/rx signals for nsgpioJosh Blum2011-07-282-2/+2
* simple_gemac: add parameter to allow disabling rx flow control at compile timeMatt Ettus2011-07-271-6/+10
* u2/u2p: apply atr/gpio changes to u2pMatt Ettus2011-07-272-14/+7
* atr: forgot to delete this lineMatt Ettus2011-07-271-1/+0
* u2: redo the atr gpio pins, remove some old cruftMatt Ettus2011-07-272-52/+48
* u2p: finish copying over serdes light fixMatt Ettus2011-07-221-2/+1
* u2/u2p: further qualify the serdes link lightMatt Ettus2011-07-213-7/+13
* usrp2: split inspection logic into each relevant cycleJosh Blum2011-07-191-11/+35
* appease the ISE godsMatt Ettus2011-07-195-2/+5
* removed wb readback of ATR, allowing it to be synthesized as lutsMatt Ettus2011-07-192-4/+10
* N200: detailed map report allows you to see what takes up too much spaceMatt Ettus2011-07-194-0/+4
* dsp: reduce bitwidth to help timingMatt Ettus2011-07-191-4/+6
* fpga: print timing report after generate bin fileJosh Blum2011-07-192-1/+34
* dsp: reset the interpolator when the rate changes, to prevent oscillationMatt Ettus2011-07-191-7/+8
* b100: fix for fpga syntax error on xfer_rateJosh Blum2011-07-191-1/+1
* Merge branch 'b100_shrink' into new_workJosh Blum2011-07-1929-718/+967
|\
| * usrp2: split compat number into major/minor (increment minor for fixes)Josh Blum2011-07-032-2/+2
| * e100: proc_int should be high when interruptedJosh Blum2011-06-201-3/+1
| * e100: added proc_int and buffer for async messagesJosh Blum2011-06-192-17/+49
| * u1p: remove uart and bus testing to fit easierMatt Ettus2011-06-161-8/+9
| * u1p: remove unused portsMatt Ettus2011-06-161-1/+0
| * u1e: core compile now works as a fullchip lintMatt Ettus2011-06-161-1/+1
| * u1p/u1e: cleanup some warnings, connect the correct clocksMatt Ettus2011-06-163-12/+11
| * USRP2/N2x0: incremented compat numbers for frontend workJosh Blum2011-06-152-2/+2
| * Merge branch 'usrp_e100_aux_spi' into dsp_rebaseMatt Ettus2011-06-155-156/+24
| |\
| | * usrp-e100: removed passthrough files, not needed w/ aux spi for clock chipJosh Blum2011-06-093-139/+0
| | * usrp-e100: make reg_test32 persistent across resets, bump compat numberJosh Blum2011-06-081-2/+3
| | * usrp-e100: work on aux spiJosh Blum2011-06-082-17/+22
| * | u1e/u1p: new register map for new dspMatt Ettus2011-06-152-26/+32
| * | u1p: work in dual rx and frontend from u1eMatt Ettus2011-06-142-16/+61
| * | u1p: new tx dsp frontend, copied from u1eMatt Ettus2011-06-141-10/+17
| * | u1e-dsp: attach tx dc offset and iq balanceMatt Ettus2011-06-142-10/+14
| * | dsp: implement iqbal on txMatt Ettus2011-06-122-30/+35
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 23:51:06 +0000