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* b100/e100: bump compat minor for inversion fixJosh Blum2012-10-052-2/+2
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* e1x0: fix RX ADC I and Q inversionJosh Blum2012-10-051-2/+13
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* b100: fix RX ADC I and Q inversionJosh Blum2012-10-051-4/+4
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* e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-152-5/+5
| | | | This effectivly works around bus initial transaction issues.
* e100: reverted commit registering in gpmcJosh Blum2012-07-151-38/+1
| | | | There is a subtle bus issue that the last changset did not address.
* Added registers for gpmc-to-fifo interface to address sequence errors for ↵Al Fayez2012-05-221-1/+38
| | | | E100/E110
* e100: bump compat minor for xclock reader fixJosh Blum2012-05-101-1/+1
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* fpga: xclock fix for edge case conditionJosh Blum2012-05-081-6/+8
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* vita: moved clear register to overlap with nchan registerJosh Blum2012-04-095-6/+6
| | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
* b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-012-5/+5
| | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change.
* B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
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* fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
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* b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
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* b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
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* b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
| | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
| | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option.
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
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* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero.
* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
| | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes.
* dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
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* dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
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* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
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* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | | | all n-series devices meet timing
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested.
* dsp rework: pass enables into glue, update power trig, parameterize, fix ↵Josh Blum2012-02-109-103/+145
| | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
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* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
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* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
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* b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
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* power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
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* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0226-262/+544
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* power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
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* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
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* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
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* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
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* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
|\ | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v
| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
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| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
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| * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
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| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
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| * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
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* | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
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* | dsp_rework: handle longer headersMatt Ettus2012-01-311-2/+8
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* | dsp_rework: more thorough testMatt Ettus2012-01-311-8/+20
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* | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_bufferingJosh Blum2012-01-302-8/+13
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* | dsp rework: work on 8 to 16 engine (usrp2 ok)Josh Blum2012-01-302-25/+26
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* | dsp_engine: work with transport headerMatt Ettus2012-01-301-16/+14
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* | dsp rework: integrated dspengine_8to16, some tweaksJosh Blum2012-01-303-8/+8
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* | dsp: 8 to 16 bit conversion for tx side. believed to be functionalMatt Ettus2012-01-292-12/+230
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