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* usrp_e : Unload the module before loading the FPGA. Reload after the fpga is ...Philip Balister2010-11-092-2/+10
* usrp_e : Fix register definitions for COMPAT and others.Philip Balister2010-11-041-1/+3
* usrp_e: Comment out fpga loading until we unload module during load.Philip Balister2010-11-041-1/+2
* Merge remote branch 'origin/usrp_e_next' into usrp_e_nextPhilip Balister2010-11-04194-2958/+9736
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| * Merge branch 'next' into usrp_e_nextJosh Blum2010-10-279-146/+120
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| | * uhd: removed dilv in rx files examplesJosh Blum2010-10-272-14/+0
| | * uhd: added rx samples to udp example, cleaned up other examples, added gain o...Josh Blum2010-10-275-36/+187
| | * uhd: added rx to file example, simplified cmake file for examplesJosh Blum2010-10-272-26/+162
| | * usrp: added to subdev spec comments/docsJosh Blum2010-10-271-3/+8
| | * usrp: added a time sync check for multi usrpJosh Blum2010-10-272-0/+17
| * | usrp-e: use clock control to get clock rate, removed temporary constantJosh Blum2010-10-275-27/+18
| * | usrp-e: implemented fpga loading and compat checkingJosh Blum2010-10-276-27/+94
| * | usrp_e: added support for building fpga image into images MakefileJosh Blum2010-10-271-0/+16
| * | Merge branch 'ue1_rev2' into usrp_e_nextJosh Blum2010-10-2764-215/+3325
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| | * | allow for CS to rise before, at the same time, or after OEMatt Ettus2010-09-241-7/+6
| | * | better debug pinsMatt Ettus2010-09-232-7/+11
| | * | watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
| | * | fix timing issue on DAC outputs with rev 2. This puts the whole system on a ...Matt Ettus2010-09-212-50/+25
| | * | send all gpmc signals to mictorMatt Ettus2010-09-164-0/+201
| | * | updated pins to match rev2, removed dip switch, etc. seems to compile ok.Matt Ettus2010-09-093-137/+130
| | * | pins are different on rev2Matt Ettus2010-09-091-264/+4
| | * | fixed makefile to compile with our new systemMatt Ettus2010-09-071-44/+36
| | * | add register to tell host about compatibility level and which image we are usingMatt Ettus2010-08-301-5/+14
| | * | move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
| | * | Merge branch 'tx_policy' into u1eMatt Ettus2010-08-253-29/+23
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| | * \ \ Merge branch 'u1e_merge' into u1eMatt Ettus2010-08-2512-5605/+340
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| | | * | | no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
| | | * | | match the signal names in this designMatt Ettus2010-08-231-3/+3
| | | * | | debug pins cleanupMatt Ettus2010-08-231-3/+3
| | | * | | properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
| | | * | | catch up with tx_policyMatt Ettus2010-08-1911-5572/+311
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| | * | | attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
| | * | | connect atrMatt Ettus2010-08-171-1/+1
| | * | | delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
| | * | | this is necessary for some reasonMatt Ettus2010-08-131-1/+2
| | * | | connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
| | * | | enlarge loopback fifoMatt Ettus2010-08-101-4/+1
| | * | | Merge branch 'ise12' into u1eMatt Ettus2010-07-199-45/+163
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| | * | | | make loopback compileMatt Ettus2010-07-141-0/+3
| | * | | | Merge branch 'reload' into u1eMatt Ettus2010-07-092-5/+10
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| | * | | | | point to new location for fifosMatt Ettus2010-07-091-1/+1
| | * | | | | Merge branch 'reload' into u1eMatt Ettus2010-07-081-11/+32
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| | * \ \ \ \ \ Merge branch 'reload' into u1eMatt Ettus2010-07-071-5/+16
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| | * \ \ \ \ \ \ Merge branch 'master' into u1eMatt Ettus2010-07-061-4/+5
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| | * \ \ \ \ \ \ \ Merge branch 'master' into u1eMatt Ettus2010-06-181-1/+2
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| | * | | | | | | | | added ability to clear out fifos of tx and rx.Matt Ettus2010-06-173-28/+37
| | * | | | | | | | | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-1442-715/+672
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| | * | | | | | | | | | debug pinsMatt Ettus2010-06-101-3/+6
| | * | | | | | | | | | much bigger fifosMatt Ettus2010-06-101-2/+2
| | * | | | | | | | | | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
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