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* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
| | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes.
* dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
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* dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
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* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
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* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | | | all n-series devices meet timing
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested.
* dsp rework: pass enables into glue, update power trig, parameterize, fix ↵Josh Blum2012-02-109-103/+145
| | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
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* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
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* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
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* b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
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* power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
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* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0226-262/+544
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* power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
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* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
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* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
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* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
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* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
|\ | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v
| * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
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| * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
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| * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
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| * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
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| * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
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* | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
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* | dsp_rework: handle longer headersMatt Ettus2012-01-311-2/+8
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* | dsp_rework: more thorough testMatt Ettus2012-01-311-8/+20
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* | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_bufferingJosh Blum2012-01-302-8/+13
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* | dsp rework: work on 8 to 16 engine (usrp2 ok)Josh Blum2012-01-302-25/+26
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* | dsp_engine: work with transport headerMatt Ettus2012-01-301-16/+14
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* | dsp rework: integrated dspengine_8to16, some tweaksJosh Blum2012-01-303-8/+8
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* | dsp: 8 to 16 bit conversion for tx side. believed to be functionalMatt Ettus2012-01-292-12/+230
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* | dsp rework: increase the number of effective bits in the duc scale factorJosh Blum2012-01-281-1/+1
| | | | | | | | This will be useful for effecting the dynamic range of the sc8 tx mode.
* | dsp rework: added double buffer interface to vita txJosh Blum2012-01-285-12/+41
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* | dsp rework: moved scale and round into ddc chainJosh Blum2012-01-287-41/+49
| | | | | | | | 16to8 engine now performs only a clip from 16->8
* | dsp rework: top level fixes B100/E100Josh Blum2012-01-274-8/+9
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* | dsp rework: integrated custom dsp module shellsJosh Blum2012-01-2718-38/+370
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* | dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-2710-106/+203
| | | | | | | | added user registers into each toplevel (not used yet)
* | dsp rework: renamed dsp signals for frontend IOJosh Blum2012-01-276-32/+66
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* | dsp rework: u2_core test implementationJosh Blum2012-01-2613-446/+49
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* n2xx: updated bootloader to latest build in uhd masterJosh Blum2012-01-111-377/+377
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* usrp2/nseries: restored clock/serdes readbackJosh Blum2011-11-232-4/+4
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* need more umph out of correction valuesJosh Blum2011-11-106-8/+8
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* remove unused irq to meet timingJosh Blum2011-11-052-21/+7
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* convenience makefiles for top level projectsJosh Blum2011-11-052-0/+31
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* increase vita rx fifosize to 10, like USRP2, make things workJosh Blum2011-11-042-4/+4
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* dsp: remove dsp_buffer and replace with simpler add_routing_header,Matt Ettus2011-11-043-3/+50
| | | | other funcs of dsp_buffer are done by double_buffer and dsp_engine
* dsp: remove warningsMatt Ettus2011-11-042-4/+6
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* u1e: fix unattached nets from copy-paste errorMatt Ettus2011-11-041-3/+3
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* b100: fix warnings, complete removal of test codeMatt Ettus2011-11-042-16/+7
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