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* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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* | changed commentMatt Ettus2010-05-041-1/+1
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* have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
| | | | | | | as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO
* separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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* send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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* Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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* Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
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* Register outputs to omap to prevent runt pulses from falsely triggering ↵Matt Ettus2010-04-233-7/+20
| | | | interrupts
* find time_64bitMatt Ettus2010-04-201-0/+1
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* added pps and time capabilityMatt Ettus2010-04-153-5/+21
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* access frame length regs from wishboneMatt Ettus2010-04-152-10/+18
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* async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-155-37/+72
| | | | for gpmc
* async gpmc progressMatt Ettus2010-04-154-18/+173
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* change time parameters because Xilinx IP has a 1ps timescaleMatt Ettus2010-04-151-14/+27
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* add bus error reportingMatt Ettus2010-04-151-3/+9
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* correct name of moduleMatt Ettus2010-04-151-2/+2
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* progress on synchronous gpmc, but it may not be possible due to the limited ↵Matt Ettus2010-04-153-43/+45
| | | | number of clock edges
* synchronous and asynchronous gpmc modelsMatt Ettus2010-04-153-3/+100
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* handle all tri-state in the top level of gpmcMatt Ettus2010-04-153-6/+8
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* more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
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* more progress on synchronous interfaceMatt Ettus2010-04-144-26/+95
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* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-142-3/+3
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* make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
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* added in a loopback fifoMatt Ettus2010-04-141-4/+11
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* probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
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* minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
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* lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
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* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
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* split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
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* added 16-bit wide atr controllerMatt Ettus2010-04-015-47/+117
| | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
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* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
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* remove timescale junkMatt Ettus2010-03-265-21/+19
| | | | | | | | get rid of asynchronous resets fix spelling error corrected comment
* connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | be read/controlled from SW
* Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
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| * Merge branch 'master' into udpMatt Ettus2010-03-25221-3/+27520
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| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
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| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
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| * | Xilinx ISE is incorrectly parsing the verilog case statement, this is a ↵Matt Ettus2010-03-241-1/+7
| | | | | | | | | | | | workaround
| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
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| * | ignore emacs backup filesMatt Ettus2010-03-231-0/+1
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| * | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
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| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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| * | copy in wrong placeMatt Ettus2010-03-101-60/+0
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| * | copied over from quad radioMatt Ettus2010-02-081-0/+60
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-255-34/+103
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
| | * | speed up timing by ignoring the too_early error. We'll need to FIXME this laterMatt Ettus2010-01-191-2/+5
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| | * | Added set time and set time at next pps. Removed the old sync pps commands, ↵Josh Blum2010-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | they dont make sense to use anymore. Replaced the mimo config with clock config. The clock config handles the pps and the reference. Modified the memory map and internal calls to reflect the fpga changes.
| | * | moved around regs, added a bit to allow for alternate PPS sourceMatt Ettus2010-01-181-4/+10
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