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* uhd: filling in mimo usrp implementation, renamed get_name to get_pp_string ↵Josh Blum2010-07-059-20/+208
| | | | for simple and mimo usrp
* usrp2: removed usrp2.hpp header, its not needed, just use the ↵Josh Blum2010-07-056-79/+87
| | | | | | discovery/factory system uhd: added usrp_mimo skeleton code/header
* usrp2: some cleanup and tweaks in io implJosh Blum2010-07-051-41/+76
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* uhd: renamed the vrt header to vrt_if_packet headerJosh Blum2010-07-057-10/+10
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* usrp2: moved calculations for max packet size and otw types into shared ↵Josh Blum2010-07-054-73/+88
| | | | object between device and mboards
* usrp2: split mboard impl into its own class, usrp2 device can instantiate N ↵Josh Blum2010-07-056-224/+282
| | | | mboard impls for mimo setup (works with 1 for now)
* uhd: vrt packet handler fix and tweaksJosh Blum2010-07-051-36/+30
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* uhd: forgot burst flags, tweaks to vrt info -> metadataJosh Blum2010-07-052-5/+6
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* uhd: work vectorizing the vrt packet handler, reworked vrt packet stuff, ↵Josh Blum2010-07-059-335/+401
| | | | needs testing
* usrp2: increased transport buffer minimum size, and added warningJosh Blum2010-07-054-18/+29
| | | | | | added more notes on buffer size to the manual pulled in some firmware fixes from the mimo work, just to have them in here
* uhd: added build notes for fedora 64 boost not foundJosh Blum2010-06-281-1/+4
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* uhd: moron alert, used incorrect bounds in simd loop, the remainder loop was ↵Josh Blum2010-06-282-12/+11
| | | | doing 3/4 the work
* uhd: convert types simd, unpack with zero constant for lower halfJosh Blum2010-06-281-2/+3
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* uhd: moved convert routines into implementation header file (out of python ↵Josh Blum2010-06-283-176/+218
| | | | gen file)
* uhd: implemented complex float <-> item32 conversion with sse2Josh Blum2010-06-282-0/+84
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* uhd: replaced single sample converters with vector convertersJosh Blum2010-06-281-46/+97
| | | | easy to conditionally compile in SIMD instrinsics etc..
* uhd: removed hackery to set performance flags, use release mode.Josh Blum2010-06-262-6/+8
| | | | | | The correct optimization flags are added when the build type is set to release. Made a change to set built type to release if not specified, and added build guide notes. For MSVC, one must set release mode from the visual studio IDE.
* uhd: fix for windows warning, tweaks for msvc optimization flagsJosh Blum2010-06-252-6/+11
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* uhd: reworked time_spec_t to be more flexible: arithmetic, comparison ↵Josh Blum2010-06-248-86/+105
| | | | | | | | | operators... Replaced nsecs with fractional seconds in units of seconds. Replaced nsecs and secs members with public function members. time_spec_t has a more diverse set of constructors and methods. It can handle the cases where frac secs are greater than 1 second.
* uhd: created benchmark rx example appJosh Blum2010-06-247-13/+220
| | | | Made mods to time spec to support math operators.
* uhd: tweaks to ic regs maps common generator codeJosh Blum2010-06-222-2/+4
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* usrp2: init clock rate shadows for dboard iface, uhd: pthread sched fix ↵Josh Blum2010-06-183-3/+6
| | | | error condition check
* Merge branch 'burn_dbid' into pre_mergeJosh Blum2010-06-188-44/+343
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| * uhd: added checking for xcvr dbids, added unknown dboard rx and tx ↵Josh Blum2010-06-183-14/+301
| | | | | | | | constructors (for bad dbids or combinations)
| * uhd: added dboard manager call to register xcvr board, implemented in xcvr ↵Josh Blum2010-06-186-32/+44
| | | | | | | | dboard code
* | usrp2: updated fpga build notesJosh Blum2010-06-181-1/+1
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* | Merge branch 'uhd_fpga_merge' into pre_mergeJosh Blum2010-06-18268-901/+1835
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| * \ Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_masterJosh Blum2010-06-15268-901/+1835
| |\ \ | | | | | | | | | | | | | | | | Conflicts: fpga/.gitignore
| | * | new make works on ise12Matt Ettus2010-06-141-1/+7
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| | * | produces good bin filesMatt Ettus2010-06-114-57/+31
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| | * | first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
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| | * | get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
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| | * | move u2_core into u2_rev3 directory to simplify directory structure and save ↵Matt Ettus2010-06-085-46/+2
| | | | | | | | | | | | | | | | headaches
| | * | allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
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| | * | report ise version in buildMatt Ettus2010-06-071-1/+1
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| | * | proper name for directoryMatt Ettus2010-06-071-1/+1
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| | * | name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
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| | * | non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
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| | * | manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
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| | * | from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-273-0/+1321
| | | | | | | | | | | | | | | | non-udp versions
| | * | ignore output filesMatt Ettus2010-05-271-0/+2
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| | * | new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
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| | * | Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
| | | * | better test program for just the tx sideMatt Ettus2010-05-191-163/+63
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| | | * | fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
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| | | * | Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
| | | |\ \ | | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| | * | | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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| | * | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| | * | | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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| | * | | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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