| Commit message (Collapse) | Author | Age | Files | Lines |
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This effectivly works around bus initial transaction issues.
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There is a subtle bus issue that the last changset did not address.
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In the windows network address extractor:
The except: continue line could get use stuck in an infinite loop.
This fix sets addr to None so the code below it does not execute,
and the next node in the chain is tested as expected.
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a boolean
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This patch does not work. A possibile solution will be added to master.
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XCVR2450 has a common LO for RX and TX.
The use LO offset should be the same for both sides.
When different, a tune for one side will override the other side,
because the DSP will not know the compensation factor after the other side is tuned.
Setting both use_lo_offset to false is how this was pre 3.4 release.
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E100/E110
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This helps the case of 4x DDC no DUC for example,
that way at least something empty is set to the property.
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It is possible on some machines (at least one in this case),
for adNode to not have the attribute next. Unexplained...
This may be a fix, and if not, should be harmless.
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Its important to use a signed cast when converting float to int.
Then assign that signed int to an unsigned type of the same width.
Its undefined behaviour when converting a negative float to an unsigned int.
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These register addresses should be in hex.
Fortunately, they are not set in the code,
so the typo did not break anything in UHD.
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has_key is not in python3.0, use key in dict
put try catch around interface enumeration, might be an ipv6 issue
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The actual recv buffer will be automatically released when dereferenced.
By releasing this buffer early we allowed for a race condition:
Subsequent wrapper buffers that shared the same actual buffer
could get their memory filled by new recvd packets from the USB layer.
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given performance benchmarks involving the converter,
when the driver is also doing other things
sc8 conversions will still involve tables since
no SIMD implementations exist yet
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specified in UHD_RELEASE_MODE
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This fixes the bug where setting the format clears the vita RX.
This is only an issue when the noclear option is set by UHD,
because the format register is always so, so it always clears.
Note: noclear is there to support the backwards compat API (pre streamer).
Now, numchans and clear overlap. This is ok because
in the host code, clear and numchans are always used together.
All timing meets on N2xx and USRP2.
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This fixes the bug of unwanted clearing when setting format.
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This is a typo in the set_clock_config implementation.
However, the enum values are the same, so this would not cause a bug.
Fixed although set_clock_config is a deprecated interface.
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When exiting the read/write data state,
when the transfer count maxes out/peaks,
the fifo read/write signals were getting this
condition the cycle after with the state change.
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Fixes compilation on platforms that dont have one of the OS defines
by providing #else case for rx_dsp_buff_size constant.
This also makes OSX the special case and assumes other OS
can handle the large RX socket buffer size.
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Its important to stop the threads before we let
the other smart point objects naturally deconstruct
to avoid thread-based race conditions.
The attempt to deconstruct the tree and soft time ctrl
had a bug because the tree had references in subtrees
within the dboard manager class.
Rather than continue to fix this method and
deconstruct the tree to free up soft time ctrl,
it seems simpler to just stop the thread in soft time ctrl,
and then let it naturally deconstruct later by ref count.
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Better to give an output than just an empty pause.
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This fixes the lockup/clocking condition when the following hw combo is used:
USRP1 r4.5 + DBSRX + another i2c board
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