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* Merge branch 'refclock_docs'Josh Blum2010-11-232-5/+35
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| * Updated refclock docs for USRP1, USRP2 and N2XXJason Abele2010-11-232-5/+35
| | | | | | | | | | Added power range limits Added external refclock notes for USRP1
| * Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdprivJosh Blum2010-11-221-3/+4
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* | \ Merge branch 'fpga_flow_control' into nextJosh Blum2010-11-231-1/+1
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| * | | packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
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* | | | E100: internal ref fix switch statementNick Foster2010-11-231-3/+3
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* | | | usrp-e100: updated for building with nextJosh Blum2010-11-232-7/+5
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* | | | Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into nextJosh Blum2010-11-23273-1379/+30459
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| * | | | uhd: added new hardware to readmeJosh Blum2010-11-233-3/+8
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| * | | | usrp-n2xx: modified fw build name in makefileJosh Blum2010-11-231-3/+3
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| * | | | usrp-n210: added fpga build entry to images makefileJosh Blum2010-11-231-1/+17
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| * | | | Merge branch 'fpga_next' into nextJosh Blum2010-11-2365-878/+7961
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: fpga/usrp2/top/u1e_passthru/.gitignore fpga/usrp2/top/u1e_passthru/Makefile fpga/usrp2/top/u2plus/.gitignore fpga/usrp2/top/u2plus/Makefile usrp2/top/u1e_passthru/.gitignore usrp2/top/u1e_passthru/Makefile
| | * | | | Merge branch 'fpga_ise12' into fpga_nextJosh Blum2010-11-230-0/+0
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| | | * | | no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | generates its own flow control packets now.
| | | * | | shouldn't be executableMatt Ettus2010-11-201-0/+0
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| | | * | | modernize the testbenchMatt Ettus2010-11-191-18/+30
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| | | * | | get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
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| | | * | | fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
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| | | * | | simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-132-4/+27
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| | | * | | we're still on version 12.1Matt Ettus2010-11-132-2/+2
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| | | * | | Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
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| | | * | | reset properlyMatt Ettus2010-11-111-0/+1
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| | | * | | compiles with new file locationsMatt Ettus2010-11-111-1/+1
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| | | * | | handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
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| | | * | | clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-115-24/+25
| | | | | | | | | | | | | | | | | | | | | | | | reset to make sure it is in the correct clock domain.
| | | * | | added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-113-29/+27
| | | | | | | | | | | | | | | | | | | | | | | | style fifo in rx.
| | | * | | gray code address for emiMatt Ettus2010-11-111-1/+7
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| | | * | | fifo randomizer for emiMatt Ettus2010-11-115-4/+108
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| | | * | | now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
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| | | * | | don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
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| | | * | | don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
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| | | * | | proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
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| | | * | | cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
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| | | * | | increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
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| | | * | | switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
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| | | * | | send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
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| | | * | | typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
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| | | * | | separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-114-25/+43
| | | | | | | | | | | | | | | | | | | | | | | | without flow control
| | | * | | go to the correct stateMatt Ettus2010-11-111-3/+3
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| | | * | | add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
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| | | * | | add trigger to makefileMatt Ettus2010-11-111-0/+1
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| | | * | | assign setting reg addressesMatt Ettus2010-11-111-2/+2
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| | | * | | declarationsMatt Ettus2010-11-111-2/+3
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| | | * | | checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
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| | | * | | these got dropped during the rebaseMatt Ettus2010-11-114-31/+37
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| | | * | | Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵Ian Buckley2010-11-111-49/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u2plus. Hardcoded -90 degree clcok from first DCM as final solution
| | | * | | 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable ↵Ian Buckley2010-11-1111-11/+555
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | full watermark 2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
| | | * | | 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-114-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.
| | | * | | Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
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| | | * | | Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals.
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