summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Merge branch 'master' into flow_ctrlJosh Blum2010-10-181-1/+1
|\
| * usrp2: make the booty smaller than the number of recv framesJosh Blum2010-10-161-1/+1
* | usrp2: dont need to start streaming for this hackJosh Blum2010-10-151-1/+0
* | usrp2: temp fix to send dummy packets and flush so FPGA vita machine are in k...Josh Blum2010-10-151-0/+26
* | Merge branch 'flow_ctrl_with_fpga'Josh Blum2010-10-1577-405/+11159
|\ \ | |/ |/|
| * Merge branch 'flow_control' into flow_ctrlJosh Blum2010-10-1457-256/+10817
| |\
| | * now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-10-121-6/+16
| | * don't clear out following packets on an eob ackMatt Ettus2010-10-121-1/+1
| | * don't flag an error on eob ackMatt Ettus2010-10-121-1/+1
| | * proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-10-121-1/+8
| | * cleanup for 32 bit seqnumMatt Ettus2010-10-111-4/+3
| | * increase compatibility number for flow controlMatt Ettus2010-10-111-1/+1
| | * switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-10-113-14/+16
| | * send message on eob to ack the end of transmissionMatt Ettus2010-10-111-1/+6
| | * typo which isn't caught by xilinxMatt Ettus2010-10-111-1/+1
| | * separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-10-104-25/+43
| | * go to the correct stateMatt Ettus2010-10-081-3/+3
| | * add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
| | * add trigger to makefileMatt Ettus2010-10-081-0/+1
| | * assign setting reg addressesMatt Ettus2010-10-081-2/+2
| | * declarationsMatt Ettus2010-10-081-2/+3
| | * checkpoint in flow control packet generationMatt Ettus2010-10-085-42/+147
| | * revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
| | * reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
| | * Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
| | |\
| | | * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| | * | Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-09-301-1/+1
| | * | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-09-141-12/+12
| | * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-09-014-5/+101
| | * | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ef...Ian Buckley2010-09-015-47/+60
| | |\ \
| | | * | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
| | | * | Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-08-255-46/+59
| | * | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
| | |/ /
| | * | capacity logic fixMatt Ettus2010-08-191-1/+1
| | * | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
| | * | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
| | * | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
| | |\ \
| | | * | Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-08-199-238/+115
| | * | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
| | |\ \ \
| | * \ \ \ Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
| | |\ \ \ \
| | * \ \ \ \ Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-1610-33/+180
| | |\ \ \ \ \ | | | |_|_|/ / | | |/| | | |
| | * | | | | Regenerated FIFO's for extfifo.Ian Buckley2010-08-1212-728/+19
| | * | | | | Edited FIFO instance to delete port that was not regenerated after reconfigur...Ian Buckley2010-08-121-1/+0
| | * | | | | Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-08-125-0/+808
| | * | | | | Bringing all coregen files checked in into syncIan Buckley2010-08-1210-137/+60
| | * | | | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv in...Ian Buckley2010-08-1218-41/+587
| | |\ \ \ \ \
| | | * | | | | checkin of generated coregen filesMatt Ettus2010-08-1118-8/+556
| | * | | | | | Found bug due to not accounting for the correct number of possible in flight ...Ian Buckley2010-08-127-49/+113
| | |/ / / / /
| | * | | | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-07-3119-238/+7327
| | * | | | | Checkpoint checkin.Ian Buckley2010-07-2913-0/+1507
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 21:48:00 +0000