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* typo which isn't caught by xilinxMatt Ettus2010-10-111-1/+1
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* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-10-104-25/+43
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* go to the correct stateMatt Ettus2010-10-081-3/+3
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* add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
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* add trigger to makefileMatt Ettus2010-10-081-0/+1
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* assign setting reg addressesMatt Ettus2010-10-081-2/+2
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* declarationsMatt Ettus2010-10-081-2/+3
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* checkpoint in flow control packet generationMatt Ettus2010-10-085-42/+147
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* revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
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* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
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* Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
|\ | | | | | | | | | | | | * ise12: fix timing problem on DAC output bus clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
| * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
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| * clean up DAC inversion and swapping to match schematicsMatt Ettus2010-08-251-3/+6
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| * Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-253-27/+18
| | | | | | | | widened muxes to 4 bits to match tx side and handle more ADCs in future
| * Merge branch 'features' into tx_policyMatt Ettus2010-08-172-3/+6
| |\ | | | | | | | | | | | | | | | * features: added compat number to usrp2 readback mux makefile dependency fix for second expansion
* | | Modified phase shift of DCM1 to -64 which is intended to give more timing ↵Ian Buckley2010-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | | margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
* | | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵Ian Buckley2010-09-141-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
* | | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-09-014-5/+101
| | | | | | | | | | | | | | | | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
* | | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ↵Ian Buckley2010-09-015-47/+60
|\ \ \ | | | | | | | | | | | | efifo_merge
| * | | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
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| * | | Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-08-255-46/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
* | | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
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* | | capacity logic fixMatt Ettus2010-08-191-1/+1
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* | | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
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* | | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
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* | | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_efifo_work: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Conflicts: usrp2/vrt/vita_tx_deframer.v
| * | | Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-08-199-238/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
* | | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | * features: added compat number to usrp2 readback mux makefile dependency fix for second expansion
| * | | added compat number to usrp2 readback muxJosh Blum2010-08-091-2/+5
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| * | | makefile dependency fix for second expansionJosh Blum2010-08-091-1/+1
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* | | | Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'tx_policy' into ise12_efifo_work * tx_policy: rx error context packets should not be marked as errors in the fifo provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host checkpoint. New context packet generator to report underruns and other errors Conflicts: usrp2/top/u2_rev3/u2_core_udp.v
| * | | rx error context packets should not be marked as errors in the fifoMatt Ettus2010-08-111-1/+1
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| * | provide a way to get out of the error state without processor interventionMatt Ettus2010-07-291-1/+4
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| * | sequence number reset upon programming streamidMatt Ettus2010-07-282-5/+11
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| * | attempt at avoiding infinite error messagesMatt Ettus2010-07-281-5/+14
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| * | implemented "next packet" and "next burst" policiesMatt Ettus2010-07-283-24/+50
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| * | sequence errors can happen on start of burst as well.Matt Ettus2010-07-281-1/+1
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| * | more informative error codesMatt Ettus2010-07-282-6/+8
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| * | cleaner error handlingMatt Ettus2010-07-281-27/+28
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| * | introduce new error typesMatt Ettus2010-07-283-34/+80
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| * | test mux and gen_context_pktMatt Ettus2010-07-281-3/+22
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| * | this is an output file, it shouldn't be checked inMatt Ettus2010-07-281-5506/+0
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| * | insert protocol engine flags when requestedMatt Ettus2010-07-281-2/+6
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| * | move the streamid so it isn't at the same address as clear_stateMatt Ettus2010-07-282-2/+2
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| * | connect the demuxMatt Ettus2010-07-281-1/+1
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| * | fix a typoMatt Ettus2010-07-283-4/+4
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| * | tx error packets now muxed into the ethernet stream back to the hostMatt Ettus2010-07-284-47/+66
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| * | checkpoint. New context packet generator to report underruns and other errorsMatt Ettus2010-07-282-0/+107
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* | | Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-1610-33/+180
|\| | | |/ |/| | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet fix to stop endless error packets updated tests to match new features error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets reload bit for vita rx ctrl
| * move declaration ahead of useMatt Ettus2010-07-191-5/+5
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