| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
| |
|
| |
|
|
|
|
| |
and timing
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
|
| |
created new component wb_readback_mux_16LE.v for 16 wide bus
connected vita time pps to vita time controller and readbacks
|
| |
|
| |
|
| |
|
| |
|
| |
|
|\
| |
| |
| |
| |
| | |
Conflicts:
usrp2/top/u2_rev3/u2_core.v
usrp2/top/u2plus/u2plus_core.v
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
| |
| |
| | |
underruns. There is a timeout so it won't go forever.
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
| |
| |
| | |
a single buffer.
|
| | |
|
| | |
|
|\ \ |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| |/ |
|
| | |
|
| |
| |
| |
| | |
without debug
|
| |
| |
| |
| |
| |
| |
| | |
added stack start signal to zpu
removed wb perifs in n210 out of 0-16k
added reset controller for main app
rewire cpu addr line after booted use 0-16k
|
| | |
|
|\ \ |
|