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| | * power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
| | * dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0226-262/+544
| | * power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
| | * dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
| | * dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
| | * dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
| | * Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
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| | | * Fix missing B100 core_compile (poor Git hygeine)Nick Foster2012-01-231-0/+1
| | | * b100: bumped fpga compat number for slave fifo modeJosh Blum2012-01-121-1/+1
| | | * Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
| | | * B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-122-5/+5
| | | * Squashed slave mode changes onto master.Nick Foster2012-01-127-34/+507
| | * | dsp rework: paramaterize post_engine_bufferingJosh Blum2012-02-013-4/+16
| | * | dsp_rework: handle longer headersMatt Ettus2012-01-311-2/+8
| | * | dsp_rework: more thorough testMatt Ettus2012-01-311-8/+20
| | * | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_bufferingJosh Blum2012-01-302-8/+13
| | * | dsp rework: work on 8 to 16 engine (usrp2 ok)Josh Blum2012-01-302-25/+26
| | * | dsp_engine: work with transport headerMatt Ettus2012-01-301-16/+14
| | * | dsp rework: integrated dspengine_8to16, some tweaksJosh Blum2012-01-303-8/+8
| | * | dsp: 8 to 16 bit conversion for tx side. believed to be functionalMatt Ettus2012-01-292-12/+230
| | * | dsp rework: increase the number of effective bits in the duc scale factorJosh Blum2012-01-281-1/+1
| | * | dsp rework: added double buffer interface to vita txJosh Blum2012-01-285-12/+41
| | * | dsp rework: moved scale and round into ddc chainJosh Blum2012-01-287-41/+49
| | * | dsp rework: top level fixes B100/E100Josh Blum2012-01-274-8/+9
| | * | dsp rework: integrated custom dsp module shellsJosh Blum2012-01-2718-38/+370
| | * | dsp rework: implemented dsp changes for other top levelsJosh Blum2012-01-2710-106/+203
| | * | dsp rework: renamed dsp signals for frontend IOJosh Blum2012-01-276-32/+66
| | * | dsp rework: u2_core test implementationJosh Blum2012-01-2613-446/+49
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| * | dsp rework: fix for vita occ trailer packingJosh Blum2012-02-171-1/+1
| * | dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-152-5/+8
| * | uhd: added async md user payload and common utilsJosh Blum2012-02-145-48/+100
| * | b100: use frame boundary to calculate frame sizeJosh Blum2012-02-142-4/+6
| * | b100: reset/reenumerate fx2 for bad endpoint stateJosh Blum2012-02-143-0/+31
| * | b100: added transport flushes and moved around reset codeJosh Blum2012-02-143-13/+7
| * | dsp rework: minor fix sph, set has time spec for tsf onlyJosh Blum2012-02-141-2/+2
| * | uhd: inline time spec accessors for minor improvementJosh Blum2012-02-132-15/+18
| * | uhd: add over-the-wire option to tx waveformsJosh Blum2012-02-121-2/+3
| * | b100/usrp1: various tweaks for compiler warns and valgrindJosh Blum2012-02-094-9/+10
| * | uhd: various tweaks for compiler warns and valgrindJosh Blum2012-02-099-19/+28
| * | uhd: fixed sse2 conversion fc32 to sc8_item32_beJosh Blum2012-02-091-2/+2
| * | uhd: fixed orc conversion fc32 to sc8_item32_beJosh Blum2012-02-091-1/+1
| * | B100: Firmware reset tweaks.Nick Foster2012-02-093-48/+30
| * | uhd: added sse2 conversions for fc32 to sc8Josh Blum2012-02-082-0/+151
| * | uhd: added sse2 conversions for fc64 to sc8Josh Blum2012-02-085-10/+167
| * | Add Orc functions to convert to sc8. bswap version is a bit of a hack.Nick Foster2012-02-082-0/+28
| * | e100: loopback test fix after register tweaksJosh Blum2012-02-081-2/+1
| * | uhd: better quantization check for convert testJosh Blum2012-02-081-4/+5
| * | uhd: added sc8 conversion testsJosh Blum2012-02-074-10/+139
| * | dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0620-109/+120
| * | B100: use FPGA external reset on initNick Foster2012-02-063-1/+13
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