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* usrp2: increment fpga and fw compat numbersJosh Blum2011-03-171-2/+2
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* usrp2: use new and common slave base map for usrp2/n210Josh Blum2011-03-164-172/+115
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* usrp2: cleanup checksum code and fix precompute checksum bugJosh Blum2011-03-161-14/+9
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* usrp2: use the proper lwip macros to set the ip headerJosh Blum2011-03-151-11/+11
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* usrp2: moved sregs in host code, simplfy reg struct a littleJosh Blum2011-03-152-87/+80
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* usrp2: moved sregs in fw memory map, new framer register tableJosh Blum2011-03-154-233/+162
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* usrp2: common memory map, define slave bases in different headersJosh Blum2011-03-159-809/+154
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* usrp2: fixed mtu discovery bug, was using the last failed valueJosh Blum2011-03-141-15/+11
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* usrp_e1xx : Remove reset offset from register map.Philip Balister2011-03-141-1/+0
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* Merge branch 'windows_fix' into nextJosh Blum2011-03-141-2/+3
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| * usrp2: minor fix to use more ntohlJosh Blum2011-03-141-2/+3
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* | usrp_e : Remove commented out FPGA reset code.Philip Balister2011-03-141-3/+0
|/ | | | | | The reset is done in the device driver open. Reseting from uhd is bad because the driver has to re-initialize the spi and i2c controllers after resetting the fpga.
* usrp2: clip the mtu discovery if its within default MTU + a fewJosh Blum2011-03-131-0/+6
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* uhd: make CMAKE_BUILD_TYPE a visible variable in the guiJosh Blum2011-03-131-0/+1
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* usrp2: also store expected_time in-between statesJosh Blum2011-03-111-4/+5
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* uhd: created rx_multi_samples for multi-channel exampleJosh Blum2011-03-114-14/+161
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* uhd: cleanup/tweaks on timed samples examplesJosh Blum2011-03-113-50/+63
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* uhd: offer alternative named for python binary (seen on ubuntu server)Josh Blum2011-03-111-1/+1
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* uhd: added continuous streaming and new options to tx_waveformsJosh Blum2011-03-113-27/+55
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* uhd: a lot of tweaking, new parameters, and sig handler for to/from file ↵Josh Blum2011-03-112-33/+98
| | | | examples
* uhd: created tx_samples_from_file.cpp and added to rx_samples_to_file.cppJosh Blum2011-03-113-42/+162
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* usrp2: bump up timeout on mtu discovery (seen to be a bit too small on ↵Josh Blum2011-03-111-1/+1
| | | | windows vbox)
* uhd: only specify BOOST_SP_USE_QUICK_ALLOCATOR for the lib, apps can be ↵Josh Blum2011-03-112-4/+4
| | | | built without it
* uhd-images: specify CPACK_PACKAGE_FILE_NAME so files names are platform ↵Josh Blum2011-03-101-1/+2
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* usrp-e100: fpga fix removed missing directory from includeJosh Blum2011-03-101-1/+0
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* Merge branch 'packet_router_2nd_dsp' into nextJosh Blum2011-03-1050-2153/+1096
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| * fix: vita_rx_chain1 should use unit2 (since err0 uses unit1)Josh Blum2011-03-082-2/+2
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| * packet_router: created packet dispatcher component to replace packet ↵Josh Blum2011-03-083-236/+293
| | | | | | | | inspector in router
| * first cut at 36:72 and 72:36 for extra wide fifos. untestedMatt Ettus2011-03-072-0/+188
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| * u2/u2p: proper connections for dsp_framerMatt Ettus2011-03-072-1/+3
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| * u2/u2p: fix off-by-one error in dsp_framerMatt Ettus2011-03-061-1/+2
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| * u2/u2p: enlarge dsp rx fifos to handle jumbo frames, enable in u2plus as wellMatt Ettus2011-03-052-20/+8
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| * u2/u2p: removed redundant shortfifos from udp path (they are in the size ↵Matt Ettus2011-03-051-17/+5
| | | | | | | | adapters now)
| * u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-055-55/+26
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| * u2/u2p: rework ports againMatt Ettus2011-03-041-3/+3
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| * u2/u2p: reworked port names on packet_routerMatt Ettus2011-03-041-3/+3
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| * u2/u2p: reworked dsp framer to work more like a fifo, and do vita length ↵Matt Ettus2011-03-041-87/+56
| | | | | | | | correction
| * u2/u2p: allow cpu to receive or send packets longer than the buffer size.Matt Ettus2011-03-041-7/+10
| | | | | | | | on reception, the rest is dropped. On sending, the rest is a repeat of the buffer.
| * make fifo36_to_ll8 properly handle partial end lines.Matt Ettus2011-03-042-152/+31
| | | | | | | | I could swear I've fixed this before...
| * Merge branch 'gpmc_testing' into ethfifo_reorgMatt Ettus2011-03-0314-174/+243
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * gpmc_testing: timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity. correct port names fifo36_mux now has shortfifos on the input ports as well as output timed tester : Bring out src/dst flags for rx chain for testing. u1e: hook up tester controls move declarations to before use hook up under/overruns for debug purposes e100: integrate loopback and timed testing into main image Fix endianess for packet length and sequence number for e100 timed image. put these files in the right place. newfifo is long gone.
| | * timed packet generator : Temporarily use a checksum rather than a crc to ↵Philip Balister2011-02-261-3/+9
| | | | | | | | | | | | validate packet integrity.
| | * correct port namesMatt Ettus2011-02-251-2/+2
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| | * fifo36_mux now has shortfifos on the input ports as well as outputMatt Ettus2011-02-253-18/+28
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| | * timed tester : Bring out src/dst flags for rx chain for testing.Philip Balister2011-02-252-1/+15
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| | * u1e: hook up tester controlsMatt Ettus2011-02-172-9/+13
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| | * move declarations to before useMatt Ettus2011-02-161-8/+8
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| | * hook up under/overruns for debug purposesMatt Ettus2011-02-162-8/+12
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| | * e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-165-81/+112
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| | * Fix endianess for packet length and sequence number for e100 timed image.Philip Balister2011-02-161-8/+8
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| | * put these files in the right place. newfifo is long gone.Matt Ettus2011-02-169-5/+5
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