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* made a new block ram based fifo, 64 (65) elements long, all fifos now have "e...Matt Ettus2009-09-0328-155/+652
* bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
* major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
* cleaning up the new fifosMatt Ettus2009-09-023-155/+0
* cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an...Matt Ettus2009-09-024-56/+2
* never used, not neededMatt Ettus2009-09-024-441/+0
* debug pins, cleaned ignoresMatt Ettus2009-09-023-9/+22
* sort out active-low lines on locallink fifos, added debug pinsMatt Ettus2009-09-021-3/+15
* Removed these files completely, they were for the old style of fifosMatt Ettus2009-09-024-497/+0
* fixed addressing of registers, and added write enables to those that were mis...Matt Ettus2009-09-011-6/+9
* Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-3125-957/+693
* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-1321-0/+331
* Add custom FPGA build.jcorgan2009-07-3012-3/+1704
* Fix swapped signals.jcorgan2009-04-272-2/+3
* Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPG...jcorgan2009-04-228-0/+776
* mostly formatting and name changes. commented out special purpose pins.matt2009-04-121-180/+180
* from u2p2, autogeneratedmatt2009-04-121-279/+353
* now handles odd length packetsmatt2009-04-061-6/+9
* basic wrapper workingmatt2009-04-043-9/+240
* Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and strea...jcorgan2009-04-042-2/+23
* first cut at a wishbone interface and wrapping the corematt2009-04-044-6/+221
* copied over from other eth corematt2009-04-044-0/+928
* reset synchronizermatt2009-04-041-0/+16
* made pause enabling a pin so we can set itmatt2009-04-032-5/+4
* Properly signals an error and drops the remainder of the packet if there is a...matt2009-04-021-6/+12
* more thorough tests, including overrun, underrun, crc err, etc.matt2009-04-021-34/+42
* simulate a hiccup in the filling of the fifo. If long enough, will cause a t...matt2009-04-021-0/+15
* debug ports for fifo level testing. Normally I wouldn't check this in, but a...matt2009-04-021-3/+3
* Fix for fifo overruns on eth rx in full duplex. Now send re-pause long befor...matt2009-04-023-6/+14
* test multiple error typesmatt2009-04-021-6/+30
* added a state to ensure the error signal propagates, and now we assert src_rd...matt2009-04-021-9/+13
* only write one error into fifomatt2009-04-021-1/+1
* generate error signalmatt2009-04-021-3/+3
* added error output line, alternative to simultaneous sof/eofmatt2009-04-021-6/+8
* logic to interface locallink fifos to our macmatt2009-04-025-77/+264
* add fifos to interface to the macsmatt2009-04-011-8/+46
* rx seems to work. haven't test error framesmatt2009-04-012-40/+192
* address filteringmatt2009-04-011-3/+9
* only report result for 1 cyclematt2009-04-011-0/+1
* variable length delay line, based on srl16matt2009-04-011-0/+21
* now checks the crc as well for the received sidematt2009-04-011-2/+5
* checkpointmatt2009-04-011-0/+34
* we now inhibit our own sending when a received pause frame comes. _rx.v is c...matt2009-03-315-14/+66
* sample packetmatt2009-03-311-0/+66
* cleaned up a littlematt2009-03-312-38/+32
* tx should be fully working nowmatt2009-03-312-26/+34
* everything but CRCmatt2009-03-312-17/+37
* nearly therematt2009-03-312-42/+134
* work in progress on a simpler gigabit-only macmatt2009-03-306-0/+527
* copied over from other projectmatt2009-03-304-0/+927