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* | | make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
* | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
* | | probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
* | | minor changes to get it to synthesizeMatt Ettus2010-04-132-1/+4
* | | lengthened delay between cycles, added more transactions on the data busMatt Ettus2010-04-121-2/+7
* | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-123-120/+117
* | | split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
* | | added 16-bit wide atr controllerMatt Ettus2010-04-015-47/+117
* | | 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
* | | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
* | | remove timescale junkMatt Ettus2010-03-265-21/+19
* | | connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
* | | Merge branch 'udp' into u1eMatt Ettus2010-03-2532-132/+2545
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| * \ \ Merge branch 'master' into udpMatt Ettus2010-03-25221-3/+27520
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| * | | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-252-17/+30
| * | | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
| * | | Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka...Matt Ettus2010-03-241-1/+7
| * | | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
| * | | ignore emacs backup filesMatt Ettus2010-03-231-0/+1
| * | | more debug for fixing E'sMatt Ettus2010-03-102-6/+13
| * | | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
| * | | copy in wrong placeMatt Ettus2010-03-101-60/+0
| * | | copied over from quad radioMatt Ettus2010-02-081-0/+60
| * | | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-255-34/+103
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| | * | | speed up timing by ignoring the too_early error. We'll need to FIXME this laterMatt Ettus2010-01-191-2/+5
| | * | | Added set time and set time at next pps. Removed the old sync pps commands, t...Josh Blum2010-01-181-2/+2
| | * | | moved around regs, added a bit to allow for alternate PPS sourceMatt Ettus2010-01-181-4/+10
| | * | | remove time_sync and master_timer.Matt Ettus2010-01-183-22/+82
| | * | | allow setting time immediately in cases where there is no external pps inputMatt Ettus2010-01-181-4/+5
| | * | | allow processor to read back vrt time over readback muxMatt Ettus2010-01-181-2/+2
| | * | | proper time sync to ppsMatt Ettus2010-01-182-5/+30
| * | | | just debug pin changesMatt Ettus2010-01-252-1/+12
| * | | | typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
| * | | | moved into subdirJosh Blum2010-01-22661-491/+0
| * | | | should fix the endless packet bugMatt Ettus2010-01-181-1/+3
| * | | | yet another typoMatt Ettus2010-01-151-1/+1
| * | | | yet more debug linesMatt Ettus2010-01-152-4/+9
| * | | | typoMatt Ettus2010-01-151-1/+1
| * | | | add debug pins to find the problem with lost eof in the udp coreMatt Ettus2010-01-151-2/+2
| * | | | try a width that works...Matt Ettus2010-01-141-1/+2
| * | | | try proper resetMatt Ettus2010-01-141-1/+1
| * | | | forgot to declare wireMatt Ettus2010-01-141-1/+3
| * | | | debug stateMatt Ettus2010-01-143-5/+12
| * | | | empty file, it is actually located in the control directoryMatt Ettus2010-01-141-0/+0
| * | | | make it match the 36 bit wide versionMatt Ettus2010-01-142-6/+8
| * | | | better debug pinsMatt Ettus2010-01-052-9/+9
| * | | | more typo fixes.Matt Ettus2010-01-051-3/+3
| * | | | typo fixMatt Ettus2010-01-051-1/+1
| * | | | actually connect the ports -- why this isn't flagged as an error I'll never knowMatt Ettus2010-01-051-3/+8
| * | | | place udp core in the memory spaceMatt Ettus2010-01-052-9/+12
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