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* catch up with tx_policyMatt Ettus2010-08-1911-5572/+311
* attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
* connect atrMatt Ettus2010-08-171-1/+1
* delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
* this is necessary for some reasonMatt Ettus2010-08-131-1/+2
* connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
* enlarge loopback fifoMatt Ettus2010-08-101-4/+1
* Merge branch 'ise12' into u1eMatt Ettus2010-07-199-45/+163
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| * move declaration ahead of useMatt Ettus2010-07-191-5/+5
| * put run_tx and run_rx on the displayed LEDsMatt Ettus2010-07-191-3/+4
| * remove warningsMatt Ettus2010-07-162-3/+3
| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
| * Merge branch 'reload' into ise12Matt Ettus2010-07-154-22/+59
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| * \ Merge branch 'ise12' of ettus.sourcerepo.com:ettus/fpgapriv into ise12Matt Ettus2010-07-120-0/+0
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| | * \ Merge branch 'master' into ise12Matt Ettus2010-07-051-4/+5
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| * | \ \ Merge branch 'master' into ise12Matt Ettus2010-07-121-4/+5
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| * | | Merge branch 'master' into ise12Matt Ettus2010-06-181-1/+2
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| * | | | precompute udp checksumsMatt Ettus2010-06-151-5/+14
| * | | | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-147-275/+390
* | | | | make loopback compileMatt Ettus2010-07-141-0/+3
* | | | | Merge branch 'reload' into u1eMatt Ettus2010-07-092-5/+10
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| * | | | fix to stop endless error packetsMatt Ettus2010-07-091-2/+2
| * | | | updated tests to match new featuresMatt Ettus2010-07-092-4/+9
* | | | | point to new location for fifosMatt Ettus2010-07-091-1/+1
* | | | | Merge branch 'reload' into u1eMatt Ettus2010-07-081-11/+32
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| * | | | error packets are now valid Extension Context packetsMatt Ettus2010-07-081-11/+32
* | | | | Merge branch 'reload' into u1eMatt Ettus2010-07-071-5/+16
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| * | | | reload bit for vita rx ctrlJosh Blum2010-07-051-5/+16
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* | | | Merge branch 'master' into u1eMatt Ettus2010-07-061-4/+5
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| * | | fix bug which caused serdes fifo to disappearMatt Ettus2010-07-031-4/+5
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* | | Merge branch 'master' into u1eMatt Ettus2010-06-181-1/+2
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| * | proper dependency tracking for the makefileMatt Ettus2010-06-181-1/+2
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* | added ability to clear out fifos of tx and rx.Matt Ettus2010-06-173-28/+37
* | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-1442-715/+672
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| * new make works on ise12Matt Ettus2010-06-141-1/+7
| * produces good bin filesMatt Ettus2010-06-114-57/+31
| * first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
| * get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
| * move u2_core into u2_rev3 directory to simplify directory structure and save ...Matt Ettus2010-06-085-46/+2
* | debug pinsMatt Ettus2010-06-101-3/+6
* | much bigger fifosMatt Ettus2010-06-101-2/+2
* | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
* | proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
* | ignoresMatt Ettus2010-06-081-0/+1
* | debug pinsMatt Ettus2010-06-083-4/+10
* | Merge branch 'master' into u1eMatt Ettus2010-06-083-15/+17
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| * allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
| * report ise version in buildMatt Ettus2010-06-071-1/+1
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