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* Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-016-8/+14
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* fullchip sim now compiles again, after moving eth and models over to new ↵Matt Ettus2009-10-015-17/+159
| | | | simple_gemac
* remove unused opencoresMatt Ettus2009-10-01463-71885/+0
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* Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-302-224/+239
|\ | | | | | | | | | | | | Functionality should not change at all Conflicts: usrp2/fpga/top/u2_core/u2_core.v
| * Copied wb_1master back from quad radioMatt Ettus2009-09-302-223/+238
| | | | | | | | more sane config options, should be exactly the same memory map
* | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
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* | Merge commit 'origin' into new_ethMatt Ettus2009-09-243-11/+24
|\| | | | | | | | | Conflicts: .gitignore
| * Synchronize the internal phase of the halfband filters to the start of the ↵Matt Ettus2009-09-243-11/+24
| | | | | | | | "run" signal. This is important for MIMO. Bug reported by Christoph Hein and Hanwen .
* | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
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* | | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
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* | | remove unused portMatt Ettus2009-09-101-1/+1
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* | | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
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* | | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
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* | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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* | Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
| | | | | | | | | | | | Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though.
* | parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
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* | remove unused old style fifoMatt Ettus2009-09-041-31/+0
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* | allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
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* | debug the rx sideMatt Ettus2009-09-041-1/+6
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* | no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
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* | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
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* | MAC transmit seems to work now. The root cause of the problem was ↵Matt Ettus2009-09-034-67/+70
| | | | | | | | accidentally using the rx_clk in one stage of the fifos on the tx side.
* | set device to xc3s2000. Shouldn't make any differences.Matt Ettus2009-09-031-2/+2
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* | misc ignoresMatt Ettus2009-09-032-0/+3
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* | made a new block ram based fifo, 64 (65) elements long, all fifos now have ↵Matt Ettus2009-09-0328-155/+652
| | | | | | | | "enhanced level logic" for accurate fullness. Maybe this will help...
* | bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
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* | major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
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* | cleaning up the new fifosMatt Ettus2009-09-023-155/+0
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* | cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v ↵Matt Ettus2009-09-024-56/+2
| | | | | | | | and fifo_2clock.v are empty
* | never used, not neededMatt Ettus2009-09-024-441/+0
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* | debug pins, cleaned ignoresMatt Ettus2009-09-023-9/+22
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* | sort out active-low lines on locallink fifos, added debug pinsMatt Ettus2009-09-021-3/+15
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* | Removed these files completely, they were for the old style of fifosMatt Ettus2009-09-024-497/+0
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* | fixed addressing of registers, and added write enables to those that were ↵Matt Ettus2009-09-011-6/+9
| | | | | | | | missing. MDIO seems ok.
* | Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-3125-957/+693
|/ | | | | | | * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz.
* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-1321-0/+331
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* Add custom FPGA build.jcorgan2009-07-3012-3/+1704
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a custom build for USRP2 FPGA. It allows using a BasicRX or LFRX board and feed two independent, real signals. In addition, instead of the CIC/HB decimator, which optimizes frequency response, it uses an integrate and dump decimator, which optimizes for time-domain impulse response. These changes have been made in dsp_core_rx.v: * A second DDC has been added, sharing a frequency register with the existing DDC. * The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... into the receive FIFO. This limits the host configured decimation to 8 intead of 4. Use gr.deinterleave to recover the streams. * The ADCs are hardcoded: RX_A ==> DDC #1 I-input 0 ==> DDC #1 Q-input RX_B ==> DDC #2 I-input 0 ==> DDC #2 Q-input Thus, the input mux has been disabled. * The CIC/HB decimator has been replaced by an integrate and dump at the decimation rate. * To assist with meeting timing, the external RAM has been disabled. The basic application is to coherently sample two real IF streams and downconvert to baseband, while minimizing the impulse response duration of the resampling filters. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11519 221aa14e-8319-0410-a670-987f0aec2ac5
* Fix swapped signals.jcorgan2009-04-272-2/+3
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10926 221aa14e-8319-0410-a670-987f0aec2ac5
* Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 ↵jcorgan2009-04-228-0/+776
| | | | | | FPGA build to use integrate-and-dump decimator instead of CIC/HB combination. This provides a much shorter time duration impulse response for the same decimation rate, at the expense of worse stop-band rejection. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10888 221aa14e-8319-0410-a670-987f0aec2ac5
* mostly formatting and name changes. commented out special purpose pins.matt2009-04-121-180/+180
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10814 221aa14e-8319-0410-a670-987f0aec2ac5
* from u2p2, autogeneratedmatt2009-04-121-279/+353
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10813 221aa14e-8319-0410-a670-987f0aec2ac5
* now handles odd length packetsmatt2009-04-061-6/+9
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10779 221aa14e-8319-0410-a670-987f0aec2ac5
* basic wrapper workingmatt2009-04-043-9/+240
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10769 221aa14e-8319-0410-a670-987f0aec2ac5
* Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and ↵jcorgan2009-04-042-2/+23
| | | | | | streaming GPIO functions for USRP2. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10766 221aa14e-8319-0410-a670-987f0aec2ac5
* first cut at a wishbone interface and wrapping the corematt2009-04-044-6/+221
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10762 221aa14e-8319-0410-a670-987f0aec2ac5
* copied over from other eth corematt2009-04-044-0/+928
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10761 221aa14e-8319-0410-a670-987f0aec2ac5
* reset synchronizermatt2009-04-041-0/+16
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10760 221aa14e-8319-0410-a670-987f0aec2ac5
* made pause enabling a pin so we can set itmatt2009-04-032-5/+4
| | | | git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10759 221aa14e-8319-0410-a670-987f0aec2ac5
* Properly signals an error and drops the remainder of the packet if there is ↵matt2009-04-021-6/+12
| | | | | | an overrun. ERROR_2 changed to ERROR2. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10751 221aa14e-8319-0410-a670-987f0aec2ac5
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