| Commit message (Expand) | Author | Age | Files | Lines |
* | allow processor to read back vrt time over readback mux | Matt Ettus | 2010-01-18 | 1 | -2/+2 |
* | proper time sync to pps | Matt Ettus | 2010-01-18 | 2 | -5/+30 |
* | cleaned up the main ibs state machine | Matt Ettus | 2009-12-14 | 1 | -9/+22 |
* | dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ... | Matt Ettus | 2009-12-14 | 3 | -10/+9 |
* | changed debug pins to see incoming data | Matt Ettus | 2009-12-12 | 1 | -3/+4 |
* | reorder the memory map | Matt Ettus | 2009-12-11 | 2 | -2/+2 |
* | put new setting reg into the address space in the right place | Matt Ettus | 2009-12-11 | 1 | -1/+1 |
* | only pull from input fifo when really consuming or pushing into the next fifo | Matt Ettus | 2009-12-11 | 1 | -1/+1 |
* | Add ability to clear state out when there is an underrun | Matt Ettus | 2009-12-11 | 1 | -1/+6 |
* | fixed typo in u2_core.v resulting in unconnected net. added debug pins | Matt Ettus | 2009-12-11 | 3 | -14/+35 |
* | ignore save files | Matt Ettus | 2009-12-09 | 1 | -0/+1 |
* | First cut at vita tx, whole thing compiles | Matt Ettus | 2009-12-09 | 3 | -27/+37 |
* | flag packets which arrive way too early so the device doesn't sit there forever. | Matt Ettus | 2009-12-09 | 1 | -2/+4 |
* | very basic packet sending works | Matt Ettus | 2009-12-09 | 2 | -140/+50 |
* | seems to correctly deframe packets. now need to consume them. | Matt Ettus | 2009-12-08 | 1 | -12/+23 |
* | progress on vita_tx. it compiles now, need to work on vita_tx_control. | Matt Ettus | 2009-12-08 | 3 | -239/+182 |
* | make the testbench work in this environment, without the crossclock settings bus | Matt Ettus | 2009-12-08 | 3 | -5/+8 |
* | be a little more PC about it | Matt Ettus | 2009-11-18 | 1 | -5/+9 |
* | mostly just copied over from the rx side. Still needs a lot of work. | Matt Ettus | 2009-11-18 | 3 | -13/+221 |
* | forgot to declare wires | Matt Ettus | 2009-11-06 | 1 | -0/+4 |
* | moved regs around for vita49 | Matt Ettus | 2009-11-05 | 2 | -12/+13 |
* | vita rx instead of rx_control. Ready for firmware testing. Misses timing by... | Matt Ettus | 2009-11-05 | 4 | -4/+48 |
* | put 64 bit timer for vita49 on the settings bus | Matt Ettus | 2009-11-05 | 3 | -8/+17 |
* | VITA49 rx (and tx skeleton) copied over from quad radio | Matt Ettus | 2009-11-05 | 7 | -0/+1026 |
* | This branch is for porting from the quad radio, and minor text cleanups | Matt Ettus | 2009-11-04 | 4 | -15/+259 |
* | earliest beta files renamed to avoid confusion | Matt Ettus | 2009-10-11 | 6 | -0/+0 |
* | Properly reset the fifos. We didn't connect before. | Matt Ettus | 2009-10-05 | 1 | -5/+5 |
* | Merge branch 'new_eth' of http://gnuradio.org/git/matt into master | Johnathan Corgan | 2009-10-01 | 613 | -90023/+2518 |
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| * | Fix warnings, mostly from implicitly defined wires or unspecified widths | Matt Ettus | 2009-10-01 | 6 | -8/+14 |
| * | fullchip sim now compiles again, after moving eth and models over to new simp... | Matt Ettus | 2009-10-01 | 5 | -17/+159 |
| * | remove unused opencores | Matt Ettus | 2009-10-01 | 463 | -71885/+0 |
| * | Merge branch 'new_wb_intercon' into new_eth | Matt Ettus | 2009-09-30 | 2 | -224/+239 |
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| | * | Copied wb_1master back from quad radio | Matt Ettus | 2009-09-30 | 2 | -223/+238 |
| * | | no idea where this came from, it shouldn't be here | Matt Ettus | 2009-09-30 | 1 | -1/+1 |
| * | | Merge commit 'origin' into new_eth | Matt Ettus | 2009-09-24 | 3 | -11/+24 |
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| * | | Merge branch 'serdes_newfifo' into new_eth | Matt Ettus | 2009-09-20 | 3 | -79/+30 |
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| | * | | Untested fixes for getting serdes onto the new fifo system. Compiles, at least | Matt Ettus | 2009-09-04 | 3 | -79/+30 |
| * | | | Remove old mac. Good riddance. | Matt Ettus | 2009-09-10 | 64 | -15211/+0 |
| * | | | remove unused port | Matt Ettus | 2009-09-10 | 1 | -1/+1 |
| * | | | More xilinx fifos, more clean up of our fifos | Matt Ettus | 2009-09-10 | 12 | -129/+555 |
| * | | | might as well use a cascade fifo to help timing and give a little more capacity | Matt Ettus | 2009-09-10 | 1 | -1/+1 |
| * | | | fix a typo which caused tx glitches | Matt Ettus | 2009-09-05 | 1 | -1/+1 |
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| * | | Implement Eth flow control using pause frames | Matt Ettus | 2009-09-04 | 5 | -73/+66 |
| * | | parameterized fifo sizes, some reformatting | Matt Ettus | 2009-09-04 | 2 | -54/+57 |
| * | | remove unused old style fifo | Matt Ettus | 2009-09-04 | 1 | -31/+0 |
| * | | allow control of whether or not to honor flow control, adds some debug lines | Matt Ettus | 2009-09-04 | 1 | -6/+16 |
| * | | debug the rx side | Matt Ettus | 2009-09-04 | 1 | -1/+6 |
| * | | no longer used, replaced by newfifo version | Matt Ettus | 2009-09-04 | 1 | -66/+0 |
| * | | seems to build a decent fpga, but still some issues with a full connection. | Matt Ettus | 2009-09-03 | 3 | -29/+36 |
| * | | MAC transmit seems to work now. The root cause of the problem was accidental... | Matt Ettus | 2009-09-03 | 4 | -67/+70 |