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* get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-063-44/+6
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* Phil wants gpio #145Matt Ettus2010-06-032-4/+4
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* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
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* Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-0111-391/+1749
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| * zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
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| * Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-284-250/+280
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | * experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-263-235/+266
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| * | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-287-26/+114
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | * | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | * fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-242-2/+5
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| | * removes the icache and pipelines the readsMatt Ettus2010-05-205-16/+98
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| * | non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
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| * | manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
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| * | from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-273-0/+1321
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| * | ignore output filesMatt Ettus2010-05-271-0/+2
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| * | new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
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| * | Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
* | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
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* | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
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* | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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* | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
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* | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-274-172/+72
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
| * | better test program for just the tx sideMatt Ettus2010-05-191-163/+63
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| * | fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
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| * | Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
| |\| | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | ignoresMatt Ettus2010-05-181-1/+1
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| * | Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
| |\ \ | | | | | | | | | | | | | | | | Conflicts: usrp2/control_lib/settings_bus.v
| * | | move dsp settings regs to reclocked setting bus. Works, gets us to within ↵Matt Ettus2010-05-122-12/+19
| | | | | | | | | | | | | | | | 18ps of passing timing
| * | | reverting logic clean up which should have made timing better, but made it ↵Matt Ettus2010-05-111-5/+12
| | | | | | | | | | | | | | | | worse instead
| * | | Merge branch 'master' into udpMatt Ettus2010-05-1111-14/+540
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| * \ \ \ Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-266-32/+47
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* | \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27235-2409/+30
|\ \ \ \ \ \ | | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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| * | | | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| * | | | | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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| * | | | | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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| * | | | | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * | | | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
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| * | | | revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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* | | | test full width packetsMatt Ettus2010-05-241-0/+27
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* | | | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | | | | | | | | | (by design)
* | | | fix double declarationMatt Ettus2010-05-211-1/+0
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* | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-202-3/+3
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* | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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* | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| * | | | better debug pinsMatt Ettus2010-05-171-6/+4
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* | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-203-34/+48
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* | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-126-66/+144
| | | | | | | | | | | | | | | | packet gen and test
* | | | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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* | | | Merge branch 'master' into u1eMatt Ettus2010-05-1217-46/+587
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