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* point to new location for fifosMatt Ettus2010-07-091-1/+1
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* Merge branch 'reload' into u1eMatt Ettus2010-07-081-11/+32
|\ | | | | | | | | * reload: error packets are now valid Extension Context packets
| * error packets are now valid Extension Context packetsMatt Ettus2010-07-081-11/+32
| | | | | | | | | | | | | | error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
* | Merge branch 'reload' into u1eMatt Ettus2010-07-071-5/+16
|\| | | | | | | | | * reload: reload bit for vita rx ctrl
| * reload bit for vita rx ctrlJosh Blum2010-07-051-5/+16
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* | Merge branch 'master' into u1eMatt Ettus2010-07-061-4/+5
|\| | | | | | | | | * master: fix bug which caused serdes fifo to disappear
| * fix bug which caused serdes fifo to disappearMatt Ettus2010-07-031-4/+5
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* | Merge branch 'master' into u1eMatt Ettus2010-06-181-1/+2
|\| | | | | | | | | * master: proper dependency tracking for the makefile
| * proper dependency tracking for the makefileMatt Ettus2010-06-181-1/+2
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* | added ability to clear out fifos of tx and rx.Matt Ettus2010-06-173-28/+37
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* | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-1442-715/+672
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
| * new make works on ise12Matt Ettus2010-06-141-1/+7
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| * produces good bin filesMatt Ettus2010-06-114-57/+31
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| * first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
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| * get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
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| * move u2_core into u2_rev3 directory to simplify directory structure and save ↵Matt Ettus2010-06-085-46/+2
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* | debug pinsMatt Ettus2010-06-101-3/+6
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* | much bigger fifosMatt Ettus2010-06-101-2/+2
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* | left something out of the sensitivity list.Matt Ettus2010-06-101-1/+1
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* | proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
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* | ignoresMatt Ettus2010-06-081-0/+1
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* | debug pinsMatt Ettus2010-06-083-4/+10
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* | Merge branch 'master' into u1eMatt Ettus2010-06-083-15/+17
|\| | | | | | | | | | | | | | | * master: allow other clock rates in vita time report ise version in build proper name for directory name build directory with ISE version name
| * allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
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| * report ise version in buildMatt Ettus2010-06-071-1/+1
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| * proper name for directoryMatt Ettus2010-06-071-1/+1
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| * name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
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* | remove double declarationMatt Ettus2010-06-061-1/+1
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* | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
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* | added little endian capability for gpmc to fifo and fifo to gpmc, since ARM ↵Matt Ettus2010-06-064-41/+51
| | | | | | | | is LE.
* | get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-063-44/+6
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* | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
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* | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
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* | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-0111-391/+1749
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| * | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
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| * | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual ↵Matt Ettus2010-05-284-250/+280
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | merge into udp version. Raw ethernet, ISE 10 -- Passes timing, works UDP, ISE 10 -- barely fails timing, works ISE 12 -- both fail timing, not tested yet. * new_ramloader: experimental mods to make ram loader fully synchronous. Based on IJB's work
| | * | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-263-235/+266
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| * | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-287-26/+114
| |\ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems to work on raw ethernet version which was automatically merged UDP version untested, and the following files were merged manually: u2_core_udp.v Makefile.udp * master_nocache: change the debug pins, which makes it more reliable. This is unnerving. fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| | * | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | * fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-242-2/+5
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| | * removes the icache and pipelines the readsMatt Ettus2010-05-205-16/+98
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| * | non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
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| * | manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
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| * | from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-273-0/+1321
| | | | | | | | | | | | non-udp versions
| * | ignore output filesMatt Ettus2010-05-271-0/+2
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| * | new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
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| * | Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
* | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
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* | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
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* | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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