uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: performed a forceful checkout of fpga to overwrite with current fpga code	Josh Blum	2010-11-23	121	-1085/+11263
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*	usrp_nxxx: software workarounds for weird power up state	Josh Blum	2010-11-23	3	-21/+38
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*	Merge branch 'flow_ctrl' into next	Josh Blum	2010-11-23	80	-371/+11313
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\| *	Firmware mem map changes for flow ctrl somehow didn't get propagated.	Nick Foster	2010-11-18	3	-2/+7
\| \| \| \| \| \| \| \|	Also removed firmware update fw rev checking -- it occurs to me that checking fw rev in order to update fw is counterproductive.
\| *	Updated fw rev number in N2XX burner.	Nick Foster	2010-11-18	1	-2/+1
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\| *	Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into flow_ctrl	Nick Foster	2010-11-17	120	-690/+8268
\| \|\ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: host/lib/transport/udp_simple.cpp host/lib/usrp/usrp2/mboard_impl.cpp host/lib/usrp/usrp2/usrp2_iface.cpp host/lib/usrp/usrp2/usrp2_regs.hpp
\| * \|	usrp2: implemented clear state for RX and TX control, and zero sample ↵	Josh Blum	2010-11-08	7	-44/+10
\| \| \| \| \| \| \| \| \| \| \| \|	command support
\| * \|	Merge branch 'master' into flow_ctrl	Josh Blum	2010-11-05	156	-4428/+1762
\| \|\ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: host/lib/usrp/usrp2/mboard_impl.cpp host/lib/usrp/usrp2/usrp2_impl.hpp
\| * \ \	Merge branch 'master' into flow_ctrl	Josh Blum	2010-10-28	15	-69/+376
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\| * \ \ \	Merge branch 'next' into flow_ctrl	Josh Blum	2010-10-27	38	-345/+1237
\| \|\ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: host/include/uhd/types/metadata.hpp
\| * \| \| \| \|	dbsrx: allow for setup time after changing the vco selection	Josh Blum	2010-10-24	1	-0/+3
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\| * \| \| \| \|	BasicRX: GPIOs now output 0 to decrease noise pickup.	Nick Foster	2010-10-22	1	-0/+5
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\| * \| \| \| \|	Merge branch 'master' into flow_ctrl	Josh Blum	2010-10-22	1	-0/+2
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\| * \| \| \| \| \|	images: remove exe bit left by some build processes	Josh Blum	2010-10-22	1	-0/+1
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\| * \| \| \| \| \|	Merge branch 'flow_control_fpga' into flow_ctrl	Josh Blum	2010-10-22	7	-115/+304
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\| \| * \| \| \| \| \|	the width of the address bus is called DEPTH, not WIDTH...	Matt Ettus	2010-10-21	1	-2/+2
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\| \| * \| \| \| \| \|	address gray coding	Matt Ettus	2010-10-21	1	-1/+7
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\| \| * \| \| \| \| \|	slow slew rate and lower drive to 8ma on RAM_XX signals to reduce emi	Matt Ettus	2010-10-21	1	-43/+43
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\| \| * \| \| \| \| \|	should combine the randomizer with flow_control	Matt Ettus	2010-10-21	5	-71/+254
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\| * \| \| \| \| \| \|	Merge branch 'garp' into flow_ctrl	Josh Blum	2010-10-22	6	-102/+145
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\| * \ \ \ \ \ \ \	Merge branch 'usrp2_overflow' into flow_ctrl	Josh Blum	2010-10-21	4	-2/+19
\| \|\ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: host/lib/usrp/usrp2/usrp2_impl.hpp
\| * \ \ \ \ \ \ \ \	Merge branch 'master' into flow_ctrl	Josh Blum	2010-10-21	33	-718/+2166
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\| * \ \ \ \ \ \ \ \ \	Merge branch 'master' into flow_ctrl	Josh Blum	2010-10-18	1	-1/+1
\| \|\ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: host/lib/usrp/usrp2/io_impl.cpp
\| * \| \| \| \| \| \| \| \| \| \|	usrp2: dont need to start streaming for this hack	Josh Blum	2010-10-15	1	-1/+0
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\| * \| \| \| \| \| \| \| \| \| \|	usrp2: temp fix to send dummy packets and flush so FPGA vita machine are in ↵	Josh Blum	2010-10-15	1	-0/+26
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	known state
\| * \| \| \| \| \| \| \| \| \| \|	Merge branch 'flow_ctrl_with_fpga'	Josh Blum	2010-10-15	77	-405/+11159
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\| \| * \ \ \ \ \ \ \ \ \ \	Merge branch 'flow_control' into flow_ctrl	Josh Blum	2010-10-14	57	-256/+10817
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\| \| \| * \| \| \| \| \| \| \| \| \|	now handles frames larger than the vita packet (i.e. with padding)	Matt Ettus	2010-10-12	1	-6/+16
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\| \| \| * \| \| \| \| \| \| \| \| \|	don't clear out following packets on an eob ack	Matt Ettus	2010-10-12	1	-1/+1
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\| \| \| * \| \| \| \| \| \| \| \| \|	don't flag an error on eob ack	Matt Ettus	2010-10-12	1	-1/+1
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\| \| \| * \| \| \| \| \| \| \| \| \|	proper triggering for interrupts generated on the dsp_clk	Matt Ettus	2010-10-12	1	-1/+8
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\| \| \| * \| \| \| \| \| \| \| \| \|	cleanup for 32 bit seqnum	Matt Ettus	2010-10-11	1	-4/+3
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\| \| \| * \| \| \| \| \| \| \| \| \|	increase compatibility number for flow control	Matt Ettus	2010-10-11	1	-1/+1
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\| \| \| * \| \| \| \| \| \| \| \| \|	switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate	Matt Ettus	2010-10-11	3	-14/+16
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\| \| \| * \| \| \| \| \| \| \| \| \|	send message on eob to ack the end of transmission	Matt Ettus	2010-10-11	1	-1/+6
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\| \| \| * \| \| \| \| \| \| \| \| \|	typo which isn't caught by xilinx	Matt Ettus	2010-10-11	1	-1/+1
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\| \| \| * \| \| \| \| \| \| \| \| \|	separated flow control and error reporting on tx path. should work with and ↵	Matt Ettus	2010-10-10	4	-25/+43
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	without flow control
\| \| \| * \| \| \| \| \| \| \| \| \|	go to the correct state	Matt Ettus	2010-10-08	1	-3/+3
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\| \| \| * \| \| \| \| \| \| \| \| \|	add a fifo to the end of the mux to help in timing.	Matt Ettus	2010-10-08	1	-6/+13
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\| \| \| * \| \| \| \| \| \| \| \| \|	add trigger to makefile	Matt Ettus	2010-10-08	1	-0/+1
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\| \| \| * \| \| \| \| \| \| \| \| \|	assign setting reg addresses	Matt Ettus	2010-10-08	1	-2/+2
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\| \| \| * \| \| \| \| \| \| \| \| \|	declarations	Matt Ettus	2010-10-08	1	-2/+3
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\| \| \| * \| \| \| \| \| \| \| \| \|	checkpoint in flow control packet generation	Matt Ettus	2010-10-08	5	-42/+147
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\| \| \| * \| \| \| \| \| \| \| \| \|	revert unneeded changes and incorrect comments	Matt Ettus	2010-10-07	3	-38/+38
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\| \| \| * \| \| \| \| \| \| \| \| \|	reconnect GPIOs, remove debug pins, meets timing now	Matt Ettus	2010-10-06	1	-5/+3
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\| \| \| * \| \| \| \| \| \| \| \| \|	Merge branch 'ise12' into efifo_merge_dcm	Matt Ettus	2010-10-06	3	-29/+23
\| \| \| \|\ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* ise12: fix timing problem on DAC output bus clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
\| \| \| \| * \| \| \| \| \| \| \| \| \|	fix timing problem on DAC output bus	Matt Ettus	2010-10-01	1	-2/+2
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\| \| \| * \| \| \| \| \| \| \| \| \| \|	Modified phase shift of DCM1 to -64 which is intended to give more timing ↵	Ian Buckley	2010-09-30	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
\| \| \| * \| \| \| \| \| \| \| \| \| \|	Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵	Ian Buckley	2010-09-14	1	-12/+12
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
\| \| \| * \| \| \| \| \| \| \| \| \| \|	Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵	Ian Buckley	2010-09-01	4	-5/+101
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.