| Commit message (Expand) | Author | Age | Files | Lines |
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| * | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
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| | * | | | | add timing constraints. Just have main clock signal at 64 MHz for now. | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
| * | | | | | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 |
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| * | | | | have_space and have_packet now stay high even while busy, | Matt Ettus | 2010-05-03 | 3 | -4/+6 |
| * | | | | separate timed tx and rx instead of loopback | Matt Ettus | 2010-04-28 | 1 | -3/+51 |
| * | | | | send bus error to debug pins | Matt Ettus | 2010-04-26 | 1 | -2/+4 |
| * | | | | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 3 | -16/+21 |
| * | | | | Only allow new packets if we can fit the largest possible packet (2KB) | Matt Ettus | 2010-04-23 | 1 | -1/+1 |
| * | | | | Register outputs to omap to prevent runt pulses from falsely triggering inter... | Matt Ettus | 2010-04-23 | 3 | -7/+20 |
| * | | | | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 |
| * | | | | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 |
| * | | | | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 2 | -10/+18 |
| * | | | | async seems to work with packet lengths now. Still need to do wishbone regs ... | Matt Ettus | 2010-04-15 | 5 | -37/+72 |
| * | | | | async gpmc progress | Matt Ettus | 2010-04-15 | 4 | -18/+173 |
| * | | | | change time parameters because Xilinx IP has a 1ps timescale | Matt Ettus | 2010-04-15 | 1 | -14/+27 |
| * | | | | add bus error reporting | Matt Ettus | 2010-04-15 | 1 | -3/+9 |
| * | | | | correct name of module | Matt Ettus | 2010-04-15 | 1 | -2/+2 |
| * | | | | progress on synchronous gpmc, but it may not be possible due to the limited n... | Matt Ettus | 2010-04-15 | 3 | -43/+45 |
| * | | | | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 3 | -3/+100 |
| * | | | | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 3 | -6/+8 |
| * | | | | more sync progress. This is just a skeleton for now, with junk content | Matt Ettus | 2010-04-14 | 1 | -0/+56 |
| * | | | | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 4 | -26/+95 |
| * | | | | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 2 | -3/+3 |
| * | | | | make timing diagrams for bus transactions. Still need to do reads | Matt Ettus | 2010-04-14 | 5 | -0/+46 |
| * | | | | added in a loopback fifo | Matt Ettus | 2010-04-14 | 1 | -4/+11 |
| * | | | | probably won't be using this, and it hasn't been tested | Matt Ettus | 2010-04-14 | 1 | -0/+46 |
| * | | | | minor changes to get it to synthesize | Matt Ettus | 2010-04-13 | 2 | -1/+4 |
| * | | | | lengthened delay between cycles, added more transactions on the data bus | Matt Ettus | 2010-04-12 | 1 | -2/+7 |
| * | | | | replaced ram interface with a fifo interface. still need to do rx side | Matt Ettus | 2010-04-12 | 3 | -120/+117 |
| * | | | | split out gpmc to wishbone interface to make gpmc top level cleaner | Matt Ettus | 2010-04-12 | 1 | -0/+57 |
| * | | | | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 5 | -47/+117 |
| * | | | | 16 bit wide spi core | Matt Ettus | 2010-03-27 | 1 | -0/+182 |
| * | | | | connect up the 16 bit spi core | Matt Ettus | 2010-03-26 | 2 | -5/+4 |
| * | | | | remove timescale junk | Matt Ettus | 2010-03-26 | 5 | -21/+19 |
| * | | | | connect 2 clock gen controls and 3 status pins to the wishbone so they can be... | Matt Ettus | 2010-03-26 | 3 | -8/+26 |
| * | | | | Merge branch 'udp' into u1e | Matt Ettus | 2010-03-25 | 32 | -132/+2545 |
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| | * | | | Merge branch 'master' into udp | Matt Ettus | 2010-03-25 | 221 | -3/+27520 |
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| | * | | | moved fifos around, now easier to see where they are and how big | Matt Ettus | 2010-03-25 | 2 | -17/+30 |
| | * | | | bigger fifo on UDP TX path, to possibly fix overruns on decim=4 | Matt Ettus | 2010-03-24 | 1 | -2/+11 |
| | * | | | Xilinx ISE is incorrectly parsing the verilog case statement, this is a worka... | Matt Ettus | 2010-03-24 | 1 | -1/+7 |
| | * | | | pps and vita time debug pins | Matt Ettus | 2010-03-23 | 1 | -3/+6 |
| | * | | | ignore emacs backup files | Matt Ettus | 2010-03-23 | 1 | -0/+1 |
| | * | | | more debug for fixing E's | Matt Ettus | 2010-03-10 | 2 | -6/+13 |
| | * | | | better debug pins for going after cascading E's | Matt Ettus | 2010-03-10 | 1 | -1/+5 |
| | * | | | copy in wrong place | Matt Ettus | 2010-03-10 | 1 | -60/+0 |
| | * | | | copied over from quad radio | Matt Ettus | 2010-02-08 | 1 | -0/+60 |
| | * | | | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 5 | -34/+103 |
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| | | * | | | speed up timing by ignoring the too_early error. We'll need to FIXME this later | Matt Ettus | 2010-01-19 | 1 | -2/+5 |
| | | * | | | Added set time and set time at next pps. Removed the old sync pps commands, t... | Josh Blum | 2010-01-18 | 1 | -2/+2 |
| | | * | | | moved around regs, added a bit to allow for alternate PPS source | Matt Ettus | 2010-01-18 | 1 | -4/+10 |
