| Commit message (Expand) | Author | Age | Files | Lines |
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| * | no idea where this came from, it shouldn't be here | Matt Ettus | 2009-09-30 | 1 | -1/+1 |
| * | Merge commit 'origin' into new_eth | Matt Ettus | 2009-09-24 | 3 | -11/+24 |
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| | * | Synchronize the internal phase of the halfband filters to the start of the "r... | Matt Ettus | 2009-09-24 | 3 | -11/+24 |
| * | | Merge branch 'serdes_newfifo' into new_eth | Matt Ettus | 2009-09-20 | 3 | -79/+30 |
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| | * | | Untested fixes for getting serdes onto the new fifo system. Compiles, at least | Matt Ettus | 2009-09-04 | 3 | -79/+30 |
| * | | | Remove old mac. Good riddance. | Matt Ettus | 2009-09-10 | 64 | -15211/+0 |
| * | | | remove unused port | Matt Ettus | 2009-09-10 | 1 | -1/+1 |
| * | | | More xilinx fifos, more clean up of our fifos | Matt Ettus | 2009-09-10 | 12 | -129/+555 |
| * | | | might as well use a cascade fifo to help timing and give a little more capacity | Matt Ettus | 2009-09-10 | 1 | -1/+1 |
| * | | | fix a typo which caused tx glitches | Matt Ettus | 2009-09-05 | 1 | -1/+1 |
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| * | | Implement Eth flow control using pause frames | Matt Ettus | 2009-09-04 | 5 | -73/+66 |
| * | | parameterized fifo sizes, some reformatting | Matt Ettus | 2009-09-04 | 2 | -54/+57 |
| * | | remove unused old style fifo | Matt Ettus | 2009-09-04 | 1 | -31/+0 |
| * | | allow control of whether or not to honor flow control, adds some debug lines | Matt Ettus | 2009-09-04 | 1 | -6/+16 |
| * | | debug the rx side | Matt Ettus | 2009-09-04 | 1 | -1/+6 |
| * | | no longer used, replaced by newfifo version | Matt Ettus | 2009-09-04 | 1 | -66/+0 |
| * | | seems to build a decent fpga, but still some issues with a full connection. | Matt Ettus | 2009-09-03 | 3 | -29/+36 |
| * | | MAC transmit seems to work now. The root cause of the problem was accidental... | Matt Ettus | 2009-09-03 | 4 | -67/+70 |
| * | | set device to xc3s2000. Shouldn't make any differences. | Matt Ettus | 2009-09-03 | 1 | -2/+2 |
| * | | misc ignores | Matt Ettus | 2009-09-03 | 2 | -0/+3 |
| * | | made a new block ram based fifo, 64 (65) elements long, all fifos now have "e... | Matt Ettus | 2009-09-03 | 28 | -155/+652 |
| * | | bring the testbench files up to date | Matt Ettus | 2009-09-02 | 4 | -88/+79 |
| * | | major cleanup of 2 clock fifos | Matt Ettus | 2009-09-02 | 4 | -29/+48 |
| * | | cleaning up the new fifos | Matt Ettus | 2009-09-02 | 3 | -155/+0 |
| * | | cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an... | Matt Ettus | 2009-09-02 | 4 | -56/+2 |
| * | | never used, not needed | Matt Ettus | 2009-09-02 | 4 | -441/+0 |
| * | | debug pins, cleaned ignores | Matt Ettus | 2009-09-02 | 3 | -9/+22 |
| * | | sort out active-low lines on locallink fifos, added debug pins | Matt Ettus | 2009-09-02 | 1 | -3/+15 |
| * | | Removed these files completely, they were for the old style of fifos | Matt Ettus | 2009-09-02 | 4 | -497/+0 |
| * | | fixed addressing of registers, and added write enables to those that were mis... | Matt Ettus | 2009-09-01 | 1 | -6/+9 |
| * | | Merged SVN matt/new_eth r10782:11633 into new_eth | Johnathan Corgan | 2009-08-31 | 25 | -957/+693 |
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| * | Added git ignore files auto created from svn:ignore properties. | git repository hosting | 2009-08-13 | 21 | -0/+331 |
| * | Add custom FPGA build. | jcorgan | 2009-07-30 | 12 | -3/+1704 |
| * | Fix swapped signals. | jcorgan | 2009-04-27 | 2 | -2/+3 |
| * | Merged r10770:10887 from jcorgan/iad2 into trunk. Adds alternative USRP2 FPG... | jcorgan | 2009-04-22 | 8 | -0/+776 |
| * | mostly formatting and name changes. commented out special purpose pins. | matt | 2009-04-12 | 1 | -180/+180 |
| * | from u2p2, autogenerated | matt | 2009-04-12 | 1 | -279/+353 |
| * | now handles odd length packets | matt | 2009-04-06 | 1 | -6/+9 |
| * | basic wrapper working | matt | 2009-04-04 | 3 | -9/+240 |
| * | Merged r10712:10765 from jcorgan/gpio into trunk. Adds out-of-band and strea... | jcorgan | 2009-04-04 | 2 | -2/+23 |
| * | first cut at a wishbone interface and wrapping the core | matt | 2009-04-04 | 4 | -6/+221 |
| * | copied over from other eth core | matt | 2009-04-04 | 4 | -0/+928 |
| * | reset synchronizer | matt | 2009-04-04 | 1 | -0/+16 |
| * | made pause enabling a pin so we can set it | matt | 2009-04-03 | 2 | -5/+4 |
| * | Properly signals an error and drops the remainder of the packet if there is a... | matt | 2009-04-02 | 1 | -6/+12 |
| * | more thorough tests, including overrun, underrun, crc err, etc. | matt | 2009-04-02 | 1 | -34/+42 |
| * | simulate a hiccup in the filling of the fifo. If long enough, will cause a t... | matt | 2009-04-02 | 1 | -0/+15 |
| * | debug ports for fifo level testing. Normally I wouldn't check this in, but a... | matt | 2009-04-02 | 1 | -3/+3 |
| * | Fix for fifo overruns on eth rx in full duplex. Now send re-pause long befor... | matt | 2009-04-02 | 3 | -6/+14 |
| * | test multiple error types | matt | 2009-04-02 | 1 | -6/+30 |
