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* mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
* forgot to declare wiresMatt Ettus2009-11-061-0/+4
* moved regs around for vita49Matt Ettus2009-11-052-12/+13
* vita rx instead of rx_control. Ready for firmware testing. Misses timing by...Matt Ettus2009-11-054-4/+48
* put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-053-8/+17
* VITA49 rx (and tx skeleton) copied over from quad radioMatt Ettus2009-11-057-0/+1026
* This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-044-15/+259
* earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
* Properly reset the fifos. We didn't connect before.Matt Ettus2009-10-051-5/+5
* Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan2009-10-01613-90023/+2518
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| * Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-016-8/+14
| * fullchip sim now compiles again, after moving eth and models over to new simp...Matt Ettus2009-10-015-17/+159
| * remove unused opencoresMatt Ettus2009-10-01463-71885/+0
| * Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-302-224/+239
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| | * Copied wb_1master back from quad radioMatt Ettus2009-09-302-223/+238
| * | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
| * | Merge commit 'origin' into new_ethMatt Ettus2009-09-243-11/+24
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| * | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| | * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
| * | | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
| * | | remove unused portMatt Ettus2009-09-101-1/+1
| * | | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
| * | | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
| * | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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| * | Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
| * | parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
| * | remove unused old style fifoMatt Ettus2009-09-041-31/+0
| * | allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
| * | debug the rx sideMatt Ettus2009-09-041-1/+6
| * | no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
| * | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
| * | MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus2009-09-034-67/+70
| * | set device to xc3s2000. Shouldn't make any differences.Matt Ettus2009-09-031-2/+2
| * | misc ignoresMatt Ettus2009-09-032-0/+3
| * | made a new block ram based fifo, 64 (65) elements long, all fifos now have "e...Matt Ettus2009-09-0328-155/+652
| * | bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
| * | major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
| * | cleaning up the new fifosMatt Ettus2009-09-023-155/+0
| * | cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v an...Matt Ettus2009-09-024-56/+2
| * | never used, not neededMatt Ettus2009-09-024-441/+0
| * | debug pins, cleaned ignoresMatt Ettus2009-09-023-9/+22
| * | sort out active-low lines on locallink fifos, added debug pinsMatt Ettus2009-09-021-3/+15
| * | Removed these files completely, they were for the old style of fifosMatt Ettus2009-09-024-497/+0
| * | fixed addressing of registers, and added write enables to those that were mis...Matt Ettus2009-09-011-6/+9
| * | Merged SVN matt/new_eth r10782:11633 into new_ethJohnathan Corgan2009-08-3125-957/+693
* | | Enable pps interrupts. Not sure why they were disabled in the first place.Matt Ettus2009-09-291-3/+2
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* | Synchronize the internal phase of the halfband filters to the start of the "r...Matt Ettus2009-09-243-11/+24
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* Added git ignore files auto created from svn:ignore properties.git repository hosting2009-08-1321-0/+331
* Add custom FPGA build.jcorgan2009-07-3012-3/+1704
* Fix swapped signals.jcorgan2009-04-272-2/+3
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