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* Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27235-2409/+30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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| * added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| * added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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| * get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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| * settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
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| * revert commit 9899b81f920 which should have improved timing but didn'tMatt Ettus2010-05-131-5/+13
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* | test full width packetsMatt Ettus2010-05-241-0/+27
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* | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock ↵Matt Ettus2010-05-211-1/+8
| | | | | | | | (by design)
* | fix double declarationMatt Ettus2010-05-211-1/+0
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* | send bigger packets to reduce cpu loadMatt Ettus2010-05-202-3/+3
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* | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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* | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\ \ | | | | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| * | better debug pinsMatt Ettus2010-05-171-6/+4
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* | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-203-34/+48
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* | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-126-66/+144
| | | | | | | | packet gen and test
* | add missing signal from sensitivity listMatt Ettus2010-05-121-1/+1
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* | Merge branch 'master' into u1eMatt Ettus2010-05-1217-46/+587
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| * remove port which is no longer thereMatt Ettus2010-05-111-1/+1
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| * cleaned up the logic, this is copied over from quad radioMatt Ettus2010-05-111-13/+5
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| * allow settings bus to cross to a new clock domain, should help timing, but ↵Matt Ettus2010-05-119-0/+534
| | | | | | | | not attached yet
| * Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
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| * Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
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| * Merge commit 'upstream/master'Johnathan Corgan2010-03-092-1/+2
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| * | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
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| * | Remove some warnings in dsp_core_rxJohnathan Corgan2010-02-231-3/+7
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| * | Fix missing item on sensitivity listJohnathan Corgan2010-02-231-1/+1
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| * | Change bit width of CORDIC constants to remove meaningless warningJohnathan Corgan2010-02-231-24/+24
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| * | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs
* | | packet generator and verifier, to test gpmc and other data transfer stuffMatt Ettus2010-05-124-0/+153
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* | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵Matt Ettus2010-05-108-561/+9
| | | | | | | | | | | | safe_u1e necessary.
* | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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* | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
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* | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
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* | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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* | | | changed commentMatt Ettus2010-05-041-1/+1
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* | | have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
| | | | | | | | | | | | | | | | | | | | | as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO
* | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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* | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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* | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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* | | Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
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* | | Register outputs to omap to prevent runt pulses from falsely triggering ↵Matt Ettus2010-04-233-7/+20
| | | | | | | | | | | | interrupts
* | | find time_64bitMatt Ettus2010-04-201-0/+1
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* | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
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* | | access frame length regs from wishboneMatt Ettus2010-04-152-10/+18
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* | | async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-155-37/+72
| | | | | | | | | | | | for gpmc
* | | async gpmc progressMatt Ettus2010-04-154-18/+173
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* | | change time parameters because Xilinx IP has a 1ps timescaleMatt Ettus2010-04-151-14/+27
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