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| | * revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
| | * reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
| | * Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
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| | | * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
| | * | Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-09-301-1/+1
| | * | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-09-141-12/+12
| | * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-09-014-5/+101
| | * | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ef...Ian Buckley2010-09-015-47/+60
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| | | * | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
| | | * | Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-08-255-46/+59
| | * | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
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| | * | capacity logic fixMatt Ettus2010-08-191-1/+1
| | * | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
| | * | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
| | * | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
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| | | * | Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-08-199-238/+115
| | * | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
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| | * \ \ \ Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
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| | * \ \ \ \ Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-1610-33/+180
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| | * | | | | Regenerated FIFO's for extfifo.Ian Buckley2010-08-1212-728/+19
| | * | | | | Edited FIFO instance to delete port that was not regenerated after reconfigur...Ian Buckley2010-08-121-1/+0
| | * | | | | Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-08-125-0/+808
| | * | | | | Bringing all coregen files checked in into syncIan Buckley2010-08-1210-137/+60
| | * | | | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv in...Ian Buckley2010-08-1218-41/+587
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| | | * | | | | checkin of generated coregen filesMatt Ettus2010-08-1118-8/+556
| | * | | | | | Found bug due to not accounting for the correct number of possible in flight ...Ian Buckley2010-08-127-49/+113
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| | * | | | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-07-3119-238/+7327
| | * | | | | Checkpoint checkin.Ian Buckley2010-07-2913-0/+1507
| | * | | | | get it to buildMatt Ettus2010-07-145-5/+309
| | * | | | | moved forward from the old branchMatt Ettus2010-07-148-4/+876
| * | | | | | uhd: removed 1 sample buffers in test async messagesJosh Blum2010-10-142-8/+13
| * | | | | | usrp2: move udp port initialization into mboard impl so its done before async...Josh Blum2010-10-144-15/+16
| * | | | | | usrp2: handle destination port unreachable icmp in fw (kills streaming and up...Josh Blum2010-10-132-1/+13
| * | | | | | udp: fix to use concurrency hint, default hint is zero when no async enabledJosh Blum2010-10-132-11/+21
| * | | | | | usrp2: added docs on flow control ricer args and using usrp2 with a switchJosh Blum2010-10-136-25/+46
| * | | | | | usrp: test async messages app randomly runs testsJosh Blum2010-10-131-17/+67
| * | | | | | usrp2: increment tx sequence after commitJosh Blum2010-10-132-1/+3
| * | | | | | usrp2: register overflow, underflow, and pps level for picJosh Blum2010-10-122-2/+3
| * | | | | | uhd: test eob ack message, usrp2: remove rx drain on init with the promise of...Josh Blum2010-10-123-19/+20
| * | | | | | usrp2: enable the cycles per ack, and drain recv without the timeout (fixes p...Josh Blum2010-10-112-3/+4
| * | | | | | usrp2: use select rather than manually polling the simple udp socketJosh Blum2010-10-114-31/+26
| * | | | | | usrp2: use 32-bit flow control sequence numbersJosh Blum2010-10-113-20/+15
| * | | | | | usrp2: implemented flow control monitorJosh Blum2010-10-116-22/+110
| * | | | | | usrp2: add fc control registers, use small timeout for control packets againJosh Blum2010-10-112-11/+6
| * | | | | | usrp2: implement fc seq number on tx header packingJosh Blum2010-10-113-25/+41
* | | | | | | uhd: fix docs on boost version, also add additional version string for 1.44Josh Blum2010-10-142-2/+2
* | | | | | | Added documentation of daughterboard filter bandwidthsJason Abele2010-10-121-3/+15
* | | | | | | Enhance XCVR2450 to clip for high/low band tuning and add bandwidth propertyJason Abele2010-10-122-9/+149
* | | | | | | Merge branch 'set_bandwidth'Josh Blum2010-10-116-0/+18
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| * | | | | | | UHD: reordered MIMO set_rx_bandwidth arg orderNick Foster2010-10-112-2/+2
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