| Commit message (Collapse) | Author | Age | Files | Lines |
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Made so Makefile changes as well to get it to build
* master:
new make works on ise12
produces good bin files
first attempt at cleaning up the build system
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
Conflicts:
usrp2/fifo/fifo36_to_fifo18.v
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/Makefile.udp
usrp2/top/u2_rev3/u2_core_udp.v
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headaches
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* master:
allow other clock rates in vita time
report ise version in build
proper name for directory
name build directory with ISE version name
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is LE.
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* ise12_exp:
zero out debug pins. helps timing a little bit.
non-udp uses a different address for the tx dsp core
manual merge to use localparams from udp version
from UDP branch, changed names because I want these separate from the non-udp versions
ignore output files
new files from udp branch added to main Makefile
change the debug pins, which makes it more reliable. This is unnerving.
experimental mods to make ram loader fully synchronous. Based on IJB's work
fixes from IJB from 5/24. Basically connect unconnected wires.
removes the icache and pipelines the reads
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merge into udp version.
Raw ethernet, ISE 10 -- Passes timing, works
UDP, ISE 10 -- barely fails timing, works
ISE 12 -- both fail timing, not tested yet.
* new_ramloader:
experimental mods to make ram loader fully synchronous. Based on IJB's work
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Seems to work on raw ethernet version which was automatically merged
UDP version untested, and the following files were merged manually:
u2_core_udp.v
Makefile.udp
* master_nocache:
change the debug pins, which makes it more reliable. This is unnerving.
fixes from IJB from 5/24. Basically connect unconnected wires.
removes the icache and pipelines the reads
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non-udp versions
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* udp: (67 commits)
better test program for just the tx side
fix typo, no functionality difference
ignores
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
reverting logic clean up which should have made timing better, but made it worse instead
moved fifos around, now easier to see where they are and how big
bigger fifo on UDP TX path, to possibly fix overruns on decim=4
Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
pps and vita time debug pins
ignore emacs backup files
more debug for fixing E's
better debug pins for going after cascading E's
copy in wrong place
copied over from quad radio
just debug pin changes
typo caused the tx udp chain to be disconnected
moved into subdir
speed up timing by ignoring the too_early error. We'll need to FIXME this later
Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore.
moved around regs, added a bit to allow for alternate PPS source
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* udp:
better test program for just the tx side
fix typo, no functionality difference
ignores
move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing
reverting logic clean up which should have made timing better, but made it worse instead
Conflicts:
usrp2/control_lib/settings_bus.v
usrp2/top/u2_core/u2_core.v
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Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas
Conflicts:
usrp2/control_lib/setting_reg.v
usrp2/top/u2_core/u2_core.v
usrp2/top/u2_rev3/Makefile
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Conflicts:
usrp2/control_lib/settings_bus.v
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18ps of passing timing
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worse instead
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