| Commit message (Expand) | Author | Age | Files | Lines |
... | |
| * | | | put new setting reg into the address space in the right place | Matt Ettus | 2009-12-11 | 1 | -1/+1 |
| * | | | only pull from input fifo when really consuming or pushing into the next fifo | Matt Ettus | 2009-12-11 | 1 | -1/+1 |
| * | | | Add ability to clear state out when there is an underrun | Matt Ettus | 2009-12-11 | 1 | -1/+6 |
| * | | | fixed typo in u2_core.v resulting in unconnected net. added debug pins | Matt Ettus | 2009-12-11 | 3 | -14/+35 |
| * | | | ignore save files | Matt Ettus | 2009-12-09 | 1 | -0/+1 |
| * | | | First cut at vita tx, whole thing compiles | Matt Ettus | 2009-12-09 | 3 | -27/+37 |
| * | | | flag packets which arrive way too early so the device doesn't sit there forever. | Matt Ettus | 2009-12-09 | 1 | -2/+4 |
| * | | | very basic packet sending works | Matt Ettus | 2009-12-09 | 2 | -140/+50 |
| * | | | seems to correctly deframe packets. now need to consume them. | Matt Ettus | 2009-12-08 | 1 | -12/+23 |
| * | | | progress on vita_tx. it compiles now, need to work on vita_tx_control. | Matt Ettus | 2009-12-08 | 3 | -239/+182 |
| * | | | make the testbench work in this environment, without the crossclock settings bus | Matt Ettus | 2009-12-08 | 3 | -5/+8 |
| * | | | be a little more PC about it | Matt Ettus | 2009-11-18 | 1 | -5/+9 |
| * | | | mostly just copied over from the rx side. Still needs a lot of work. | Matt Ettus | 2009-11-18 | 3 | -13/+221 |
| * | | | forgot to declare wires | Matt Ettus | 2009-11-06 | 1 | -0/+4 |
| * | | | moved regs around for vita49 | Matt Ettus | 2009-11-05 | 2 | -12/+13 |
| * | | | vita rx instead of rx_control. Ready for firmware testing. Misses timing by... | Matt Ettus | 2009-11-05 | 4 | -4/+48 |
| * | | | put 64 bit timer for vita49 on the settings bus | Matt Ettus | 2009-11-05 | 3 | -8/+17 |
| * | | | VITA49 rx (and tx skeleton) copied over from quad radio | Matt Ettus | 2009-11-05 | 7 | -0/+1026 |
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* | | | connected spi pins, but the spi core still needs to be redone for 16 bit inte... | Matt Ettus | 2010-03-25 | 3 | -40/+60 |
* | | | debug pins | Matt Ettus | 2010-02-25 | 1 | -2/+3 |
* | | | enable was on the wrong address pin, needs to be the highest order one | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
* | | | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
* | | | gpmc debug pins | Matt Ettus | 2010-02-25 | 2 | -4/+14 |
* | | | point to the new files | Matt Ettus | 2010-02-25 | 1 | -0/+2 |
* | | | fix syntax error which icarus allowed (filed a bug with them) | Matt Ettus | 2010-02-25 | 1 | -7/+9 |
* | | | loopback and test | Matt Ettus | 2010-02-25 | 2 | -7/+38 |
* | | | corrected logic | Matt Ettus | 2010-02-25 | 1 | -17/+7 |
* | | | edge sync on done signals so we only fill/empty one buffer | Matt Ettus | 2010-02-25 | 2 | -2/+32 |
* | | | Switched xilinx primitives because they order the bits funny in the other one | Matt Ettus | 2010-02-25 | 1 | -48/+79 |
* | | | ISE chokes on the pure verilog version so we use the macro | Matt Ettus | 2010-02-25 | 1 | -4/+49 |
* | | | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 6 | -25/+165 |
* | | | Merge branch 'master' into u1e | Matt Ettus | 2010-02-23 | 2 | -1/+3 |
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| * | | proper initialization of the ram | Matt Ettus | 2010-02-23 | 2 | -1/+2 |
| * | | ignore emacs cruft | Matt Ettus | 2010-02-08 | 1 | -0/+2 |
* | | | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 3 | -6/+63 |
* | | | use our fancy new debug ports | Matt Ettus | 2010-02-23 | 1 | -0/+3 |
* | | | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 3 | -3/+68 |
* | | | remove the #1 delay in all the regs. They just slow down sims. | Matt Ettus | 2010-02-22 | 4 | -96/+90 |
* | | | Modified nsgpio.v to support 16 bit little endian bus interface. | Matt Ettus | 2010-02-22 | 1 | -0/+124 |
* | | | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 4 | -37/+54 |
* | | | added gpio control to the wishbone | Matt Ettus | 2010-02-18 | 2 | -11/+14 |
* | | | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 3 | -48/+187 |
* | | | allow default uart clock divider | Matt Ettus | 2010-02-18 | 1 | -6/+7 |
* | | | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx gl... | Matt Ettus | 2010-02-18 | 2 | -4/+7 |
* | | | speed up the presentation of registered wb data to the gpmc | Matt Ettus | 2010-02-17 | 2 | -13/+20 |
* | | | wishbone bridge now with minimal functionality. Need to check | Matt Ettus | 2010-02-16 | 8 | -11/+121 |
* | | | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 7 | -34/+160 |
* | | | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 4 | -0/+553 |
* | | | block ram interface to GPMC | Matt Ettus | 2010-02-16 | 1 | -2/+6 |
* | | | basic read support for the GPMC, responds with 16'hBEEF | Matt Ettus | 2010-02-16 | 1 | -2/+8 |