uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	usrp2: cover both rev3 cases for usrp2 revision numbers	Josh Blum	2010-11-24	1	-2/+6
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*	usrp: replace struct member sizeof with this macro so it compiles on mac	Josh Blum	2010-11-23	1	-2/+5
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*	Merge branch 'refclock_docs'	Josh Blum	2010-11-23	2	-5/+35
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\| *	Updated refclock docs for USRP1, USRP2 and N2XX	Jason Abele	2010-11-23	2	-5/+35
\| \| \| \| \| \| \| \| \| \|	Added power range limits Added external refclock notes for USRP1
\| *	Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv	Josh Blum	2010-11-22	1	-3/+4
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* \| \	Merge branch 'fpga_flow_control' into next	Josh Blum	2010-11-23	1	-1/+1
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\| * \| \|	packets are shorter now, so we need to tell the udp state machine that...	Matt Ettus	2010-11-23	1	-1/+1
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* \| \| \|	E100: internal ref fix switch statement	Nick Foster	2010-11-23	1	-3/+3
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* \| \| \|	usrp-e100: updated for building with next	Josh Blum	2010-11-23	2	-7/+5
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* \| \| \|	Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next	Josh Blum	2010-11-23	273	-1379/+30459
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\| * \| \| \|	uhd: added new hardware to readme	Josh Blum	2010-11-23	3	-3/+8
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\| * \| \| \|	usrp-n2xx: modified fw build name in makefile	Josh Blum	2010-11-23	1	-3/+3
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\| * \| \| \|	usrp-n210: added fpga build entry to images makefile	Josh Blum	2010-11-23	1	-1/+17
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\| * \| \| \|	Merge branch 'fpga_next' into next	Josh Blum	2010-11-23	65	-878/+7961
\| \|\ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Conflicts: fpga/usrp2/top/u1e_passthru/.gitignore fpga/usrp2/top/u1e_passthru/Makefile fpga/usrp2/top/u2plus/.gitignore fpga/usrp2/top/u2plus/Makefile usrp2/top/u1e_passthru/.gitignore usrp2/top/u1e_passthru/Makefile
\| \| * \| \| \|	Merge branch 'fpga_ise12' into fpga_next	Josh Blum	2010-11-23	0	-0/+0
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\| \| \| * \| \|	no need for second sequence number anymore. Each dsp tx chain	Matt Ettus	2010-11-21	2	-11/+8
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	generates its own flow control packets now.
\| \| \| * \| \|	shouldn't be executable	Matt Ettus	2010-11-20	1	-0/+0
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\| \| \| * \| \|	modernize the testbench	Matt Ettus	2010-11-19	1	-18/+30
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\| \| \| * \| \|	get rid of extraneous U messages when we actually had an ACK	Matt Ettus	2010-11-18	2	-7/+10
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\| \| \| * \| \|	fix problem with consecutive timed packets on tx	Matt Ettus	2010-11-18	1	-2/+0
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\| \| \| * \| \|	simplify time comparison to speed up logic and meet fpga timing	Matt Ettus	2010-11-13	2	-4/+27
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\| \| \| * \| \|	we're still on version 12.1	Matt Ettus	2010-11-13	2	-2/+2
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\| \| \| * \| \|	Add flow control and other small vrt fixes to u2p, minor cleanups	Matt Ettus	2010-11-11	2	-34/+38
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\| \| \| * \| \|	reset properly	Matt Ettus	2010-11-11	1	-0/+1
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\| \| \| * \| \|	compiles with new file locations	Matt Ettus	2010-11-11	1	-1/+1
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\| \| \| * \| \|	handle zero-length packets properly	Matt Ettus	2010-11-11	3	-55/+76
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\| \| \| * \| \|	clear out the vita tx chain and the tx fifo. need to check the fifo	Matt Ettus	2010-11-11	5	-24/+25
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	reset to make sure it is in the correct clock domain.
\| \| \| * \| \|	added ability to truly clear out the entire rx chain. also removed old ↵	Matt Ettus	2010-11-11	3	-29/+27
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	style fifo in rx.
\| \| \| * \| \|	gray code address for emi	Matt Ettus	2010-11-11	1	-1/+7
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\| \| \| * \| \|	fifo randomizer for emi	Matt Ettus	2010-11-11	5	-4/+108
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\| \| \| * \| \|	now handles frames larger than the vita packet (i.e. with padding)	Matt Ettus	2010-11-11	1	-6/+16
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\| \| \| * \| \|	don't clear out following packets on an eob ack	Matt Ettus	2010-11-11	1	-1/+1
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\| \| \| * \| \|	don't flag an error on eob ack	Matt Ettus	2010-11-11	1	-1/+1
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\| \| \| * \| \|	proper triggering for interrupts generated on the dsp_clk	Matt Ettus	2010-11-11	1	-1/+8
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\| \| \| * \| \|	cleanup for 32 bit seqnum	Matt Ettus	2010-11-11	1	-4/+3
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\| \| \| * \| \|	increase compatibility number for flow control	Matt Ettus	2010-11-11	1	-1/+1
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\| \| \| * \| \|	switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate	Matt Ettus	2010-11-11	3	-14/+16
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\| \| \| * \| \|	send message on eob to ack the end of transmission	Matt Ettus	2010-11-11	1	-1/+6
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\| \| \| * \| \|	typo which isn't caught by xilinx	Matt Ettus	2010-11-11	1	-1/+1
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\| \| \| * \| \|	separated flow control and error reporting on tx path. should work with and ↵	Matt Ettus	2010-11-11	4	-25/+43
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	without flow control
\| \| \| * \| \|	go to the correct state	Matt Ettus	2010-11-11	1	-3/+3
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\| \| \| * \| \|	add a fifo to the end of the mux to help in timing.	Matt Ettus	2010-11-11	1	-6/+13
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\| \| \| * \| \|	add trigger to makefile	Matt Ettus	2010-11-11	1	-0/+1
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\| \| \| * \| \|	assign setting reg addresses	Matt Ettus	2010-11-11	1	-2/+2
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\| \| \| * \| \|	declarations	Matt Ettus	2010-11-11	1	-2/+3
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\| \| \| * \| \|	checkpoint in flow control packet generation	Matt Ettus	2010-11-11	5	-42/+147
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\| \| \| * \| \|	these got dropped during the rebase	Matt Ettus	2010-11-11	4	-31/+37
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\| \| \| * \| \|	Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵	Ian Buckley	2010-11-11	1	-49/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	u2plus. Hardcoded -90 degree clcok from first DCM as final solution
\| \| \| * \| \|	1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable ↵	Ian Buckley	2010-11-11	11	-11/+555
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	full watermark 2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
\| \| \| * \| \|	1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ	Ian Buckley	2010-11-11	4	-11/+17
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.