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* log: Add DPDK version to system infomattprost2022-04-011-2/+8
| | | | | | Log installed DPDK version on boot. Signed-off-by: mattprost <matt.prost@ni.com>
* dpdk: Add support for DPDK 18.11 APImattprost2022-04-015-3/+44
| | | | | | | | Substituting old values to restore API breakage from DPDK 18.11 to DPDK 19. It is recommended at this point that users upgrade to more recent DPDK LTS versions, but the DPDK 18.11 API is functional with UHD. Signed-off-by: mattprost <matt.prost@ni.com>
* config: fix clang fallthrough syntaxMichael Dickens2022-04-011-1/+1
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* uhd: fix compiler macro orderingMichael Dickens2022-04-013-17/+17
| | | | Clang provides the same macros as GCC, so if we're differentiating between these compilers then we need to get the compiler checking macros in the correct order
* docs: add 100GigE documentationVirendra Kakade2022-04-013-9/+39
| | | | | Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
* tools: uhd_ubuntu_deb: Require --buildpathMartin Braun2022-03-311-3/+3
| | | | | | | | | | | | Because this script deletes the entire contents of --buildpath, we no longer provide '..' as the default. First, it is not a suitable default, because it will contain the directory from which this script is called. Second, if someone runs this script from a source repo for UHD, and this repo is checked out into a non-empty directory, the script will still, by default, delete all the contents from that directory. Now, the script fails when not providing --buildpath. Note that CI code is already using this command line argument.
* fpga: Update all RFNoC imagesWade Fife2022-03-3129-468/+508
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* rfnoc: Remove redundant RFNoC block descriptionsWade Fife2022-03-314-301/+0
| | | | | | | | The block descriptions radio_1x64.yml and radio_2x64.yml are subsets of radio.yml. Similarly, axi_ram_fifo_2x64.yml and axi_ram_fifo_4x64.yml are subsets of axi_ram_fifo.yml. This commit removes the redundant YAML descriptions in favor of the parameterizable versions.
* rfnoc: Update device port names in image core YAMLWade Fife2022-03-3115-704/+826
| | | | | | Update USRP RFNoC iamge core YAML files to use the more consistent device port names. Clean up the formatting and make the files more consistent.
* rfnoc: Update image builder to check for deprecated port namesWade Fife2022-03-311-1/+50
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* rfnoc: Make RFNoC device port names consistentWade Fife2022-03-3110-131/+62
| | | | | | Update all USRPs to use the same names for the same port types. For example, instead of "ctrl_port" and "ctrlport" use "ctrlport". Instead "timekeeper" and "time_keeper", use "timekeeper". Etc.
* examples: Add replay_capture.pyMartin Braun2022-03-312-0/+311
| | | | | This is an example that allows capturing RF data into DRAM, and then stream it back to host, using the Python API.
* tests: enable automated streaming tests on X410Virendra Kakade2022-03-316-30/+39
| | | | | | | | | | | | Enable automated streaming tests to run on X410. Disable tests on non-X410 devices for now. Run only DPDK tests since the setup can not withstand 4Rx 4Tx and 4FDx in non-DPDK mode in manual testing. And we need to enable running these tests for 100GbE testing. Adjust streaming test thresholds to new values which seemed to work fine in manual testing. Might make them tighter in future based on more data.
* tests: add X410 100GbE testsVirendra Kakade2022-03-311-23/+29
| | | | | | | | Disable non 100GbE X410 tests for now since the test framework currently assumes that the required bitfile(personality) is already loaded onto the device. Re-enable these tests when the above support is added. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* docs: Move X4x0 GPIO API to be subpageLane Kolbly2022-03-301-1/+1
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* fpga: ci: Add X4_400 to CI targets default listHumberto Jimenez2022-03-303-30/+35
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* python: rfnoc: Add new replay block APIs to Python APIMartin Braun2022-03-301-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | The new API calls get_{record,play}_async_metadata() calls are now available in Python. To look more Pythonic, we change the call signature and return value to either return `None` or the value (if available). For comparison, this is the C++ code: ```cpp uhd::rx_metadata_t md; if (replay_ctrl->get_record_async_metadata(md, 0.1)) { cout << "Received metadata! Error code: " << md.strerror() << endl; } else { cout << "No metadata received!" << endl; } ``` In Python, this has the more Pythonic form: ```python md = replay_ctrl.get_record_async_metadata(0.1); if md is not None: print("Received metadata! Error code: ", md.strerror()) else: print("No metadata received!") ```
* rfnoc: replay: Add ability to capture and read async infoMartin Braun2022-03-303-2/+130
| | | | | | | - Add action handlers to the replay block to store TX and RX events. - Adds two new APIs: get_{record,play}_async_metadata() to read back async info. - Add unit tests.
* tests: rfnoc: Amend mock nodes with action supportMartin Braun2022-03-301-0/+21
| | | | | | - Allow mock radios to generate mock overruns/underruns - Allow terminator blocks to inject arbitrary actions for testing purposes
* mpm: x4xx: Fix clock/time source APIMartin Braun2022-03-302-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | In f73e327, we modified PeriphManagerBase to explicitly list all required methods as per the MPM/UHD API. This had an unintended side effect: Because the clocking methods on x4xx are imported from X4xxClockMgr, and not defined on x4xx itself, the method used to import methods from X4xxClockMgr onto x4xx would refuse to re-define API calls such as set_clock_source(), get_clock_source(), and so on. The solution is to allow _add_public_methods() to overwrite existing methods, which means we can overwrite abstract methods from PeriphManagerBase in this fashion. Without this patch, UHD sessions could fail in the following manner: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=x4xx") >>> U.get_clock_source(0) Traceback (most recent call last): File "<input>", line 1, in <module> U.get_clock_source(0) RuntimeError: RuntimeError: Error during RPC call to `get_clock_source'. Error message: get_clock_source() not available on this device!
* fpga: n3xx: Add missing BIST image core headersWade Fife2022-03-296-45/+108
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* fpga: Use PROTOVER and CHDR_W from RFNoC image builderWade Fife2022-03-2913-27/+113
| | | | | | This updates all RFNoC devices so that they get the RFNoC protocol version and CHDR width in the same way, from the output generated by the RFNoC image builder.
* tests: Add complex include to resolve buildSteven Koo2022-03-291-0/+1
| | | | Signed-off-by: Steven Koo <steven.koo@ni.com>
* ci: Update commit vcpkg and CMake versionSteven Koo2022-03-294-16/+16
| | | | Signed-off-by: Steven Koo <steven.koo@ni.com>
* docs: Update E320 docsMartin Braun2022-03-281-1/+15
| | | | | - Clarify purpose of 'enclosure' flag - Add section on clock and time sync, which the E31x section already has
* mpm: e3xx: Fix get_sync_sources() APIMartin Braun2022-03-283-2/+30
| | | | | | | | | | | | | | get_sync_sources() was not implemented for E31x and E320. Because UHD assumes this exists, calling this would cause an error like this: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=e3xx") >>> U.get_sync_sources(0) Traceback (most recent call last): File "<input>", line 1, in <module> U.get_sync_sources(0) RuntimeError: rpc::timeout: Timeout of 2000ms while calling RPC function 'get_sync_sources'
* mpm: PeriphManagerBase: List all sync-related methodsMartin Braun2022-03-281-0/+59
| | | | | | | | | | All PeriphManagerBase childs need to implement - get_{clock,time,sync}_source() - get_{clock,time,sync}_sources() - set_{clock,time,sync}_source() So we populate PeriphManagerBase with defaults for all of those.
* mpm: Make default clock/time source values state-lessMartin Braun2022-03-284-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the default clock/time source is whatever the user configured in the last session. This fixes the scenario were you have any MPM device and do this: $ benchmark_rate --args $args,clock_source=external But whoops! You forgot to attach an external 10 MHz. PLL lock fails, nothing works. No worries, you run it again: $ benchmark_rate --args $args With the previous behaviour, this would retain the setting to 'external', because there's nothing to overwrite it. You would need to append `clock_source=internal` to get a working device again. Calling multi_usrp::set_clock_source("internal"), or a similar API call, might not be sufficient because the PLL lock failure might crash the program before updating the clock source is possible. The problem with this is twofold: - All non-MPM devices behave differently, i.e., they have a fixed default ('internal') which is always applied if no other option is given. This is an internal inconsistency. - Some applications (like gr-uhd's GRC bindings) simply don't set a clock/time source when selecting a "default", or they try and update the clock/time source using the API calls. Therefore, we align the behaviour of MPM devices with the other devices, and fall back to an internal source if nothing else is provided.
* mpm: e3xx: Simplify code referring to self.dboardsMartin Braun2022-03-282-42/+24
| | | | | | | | | | | | The E31x and E320 devices have one virtual daughterboard, and it is always present. This is different from N3xx, which is where the MPM code for these devices is based upon. During the E3xx initialization, we make sure that our single "daughterboard" exists and is responsive. That means we can remove some code that tests for the availability and number of daughterboards, which we need on N3xx (which works with zero, one, or two daughterboards). This also allows us some minor deduplication of code.
* fixup! uhd: add support for max10 variantsVirendra Kakade2022-03-281-2/+4
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* tests: use new args for x410 streaming testsVirendra Kakade2022-03-281-0/+6
| | | | | | | | Use new benchmark_rate args "--multi_streamer" and "--priority" for X410 streaming tests. This gets the best performance from the streaming host machine. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* fpga: n3xx: Fix clock frequency commentsWade Fife2022-03-261-2/+2
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* docs: x4xx: Remove redundant GPIO sectionLane Kolbly2022-03-251-4/+0
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* docs: rfnoc: Add doxygen tag for missing parameterMartin Braun2022-03-251-0/+1
| | | | This adds a doxygen tag for the `chan` parameter in fir_filter_block_control::set_coefficients().
* tools: Fix control packet byte enable in CHDR dissectorWade Fife2022-03-251-1/+1
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* test: x410: Add GPIO tests to X410 devtestLane Kolbly2022-03-233-6/+84
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* host: devtest: Allow getting mgmt_addr in testsLane Kolbly2022-03-231-1/+1
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* tools: Add general purpose tool for USRP configurationLars Amsel2022-03-2322-10/+510
| | | | | | | | Over the years the UHD code base got a whole bunch of tools to control and configure devices. This is an attempt to unify these tools into one. Co-authored-by: Alexander Weber <alexander.weber@ni.com>
* rfnoc: fir filter: Add support for multiple channels to block controllerJonathon Pendlum2022-03-233-133/+218
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* mpm: speed up reading gps mboard sensorsDavid Raeman2022-03-231-13/+9
| | | | | | This commit uses a more performant buffered I/O approach for reading the gpsd socket. Previously, querying a gps mboard sensor on an mpm radio would take 300-500ms due to the loop reading one byte at a time.
* images: Update manifest and compat number for X410Humberto Jimenez2022-03-232-2/+2
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* test: add support for new benchmark_rate argsVirendra Kakade2022-03-232-8/+12
| | | | | | | | Add support for the new "priority" and "multi_streamer" benchmark_rate args to run_benchmark_rate.py to enable batch runs of benchmark_rate using those arguments. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* mpm: n3xx: Recommend reboot USRP after BISTAaron Rossetto2022-03-231-1/+4
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* host: devtest: Add GPIO tests for reading back ATR settingsLane Kolbly2022-03-232-1/+30
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* mpm: x4xx: Remove GPIO classic mode registerLane Kolbly2022-03-231-12/+2
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* host: x410: Emulate GPIO classic ATR mode using new modeLane Kolbly2022-03-233-13/+83
| | | | | | This fixes an issue with setting the active channel source in MPM, and additionally allows opening up the more flexible API in the future without requiring a filesystem update.
* host: x410: Cache GPIO source in mb_controllerLane Kolbly2022-03-233-1/+12
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* Fix handling of discontinuities in power calibration dataLars Amsel2022-03-237-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power that corresponds to a certain gain values depends on the frequency band we are in. At the edges of these bands discontinuities can occur (the gain necessary to achieve the same power value changes non-continuously). The power calibration does a linear interpolation between two neighbor points in the calibration data set to find at best fitting value. We therefore have to make sure that this interpolation does not cross discontinuities. This is a minimal invasive approach. It adds values at discontinuities for the lower and the upper band. The power calibration format uses the frequency for a power to gain mapping as a map key. Therefore two gain to power mappings cannot be stored for the same frequency as it would be needed for the discontinuity. Instead the mapping for the lower band is stored at the discontinuity frequency itself. The mapping for the upper band is stored at the frequency + 1Hz. The calibration will therefore still fail to yield proper results within this sub-Hertz range. The frequency lookup in the power calibration manager now uses round instead of truncation to find the best mapping frequency in the calibration table. With this, searching for neighbor data points now ensures that the data points used belong to the same band (except for the range of (f_discontinuity, f_discontinuity + 1Hz) ). This commit does not solve the issue for calibration data generated with usrp_power_cal.py because the Python interface has no means to detect band edges for the USRP it is calibrating.
* fpga: e31x: Update DRAM IP simulationWade Fife2022-03-231-4/+22
| | | | | Update the simulation to use the renamed IP. Add ModelSim support.
* fpga: e31x: Fix DRAM traffic gen IP nameWade Fife2022-03-231-1/+1
| | | | | Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-01 05:34:31 +0000