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* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
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* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
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* cmake: Replace CMAKE_{SOURCE,BINARY}_DIR with UHD_*_DIRMartin Braun2021-09-1025-185/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | See the CMake 3.8 documentation on these two variables: https://cmake.org/cmake/help/v3.8/variable/PROJECT-NAME_SOURCE_DIR.html https://cmake.org/cmake/help/v3.8/variable/CMAKE_SOURCE_DIR.html Under normal circumstances, these two are identical. For sub-projects (i.e., when building UHD as part of something else that is also a CMake project), only the former is useful. There is no discernible downside of using UHD_SOURCE_DIR over CMAKE_SOURCE_DIR. This was changed using sed: $ sed -i "s/CMAKE_SOURCE_DIR/UHD_SOURCE_DIR/g" \ `ag -l CMAKE_SOURCE_DIR **/{CMakeLists.txt,*.cmake}` $ sed -i "s/CMAKE_BINARY_DIR/UHD_BINARY_DIR/g" \ `ag -l CMAKE_BINARY_DIR **/{CMakeLists.txt,*.cmake}` At the same time, we also replace the CMake variable UHD_HOST_ROOT (used in MPM) with UHD_SOURCE_DIR. There's no reason to have two variables with the same meaning and different names, but more importantly, this means that UHD_SOURCE_DIR is defined even in those cases where MPM calls into CMake files from UHD without any additional patches. Shoutout to GitHub user marcobergamin for bringing this up.
* fpga: Update help message for setupenv.shWade Fife2021-09-101-5/+7
| | | | | Updates the language in setupenv.sh --help to better reflect that there are many locations where Vivado is searched.
* rfnoc: Add vivado-path to rfnoc_image_builderWade Fife2021-09-102-0/+8
| | | | | | | Adds a --vivado-path option to rfnoc_image_builder that, if present, gets passed to setupenv.sh for the target device. This can be used to specify the location of Vivado if it is not installed in one of the default search locations.
* uhd: mpm: Expose filesystem version information on MPM treeLane Kolbly2021-09-081-0/+6
| | | | | This allows UHD clients to determine, for example, whether the currently loaded filesystem is up-to-date.
* python: multi_usrp: Fix overloaded function definitionMartin Anderseck2021-09-081-1/+1
| | | | | Fix function definition set_rx_iq_balance so that Python can reach the overloaded C++ function. There was a copy & paste error in there.
* radio: Improve log messages for non-implemented correctionsMartin Braun2021-09-082-5/+8
| | | | | This modifies some log messages or exception strings when using auto-correction APIs that are not supported by the underlying device.
* rh: Fix auto DC-offset correction and auto-IQ balance APIsMartin Braun2021-09-082-7/+1
| | | | | | | | N320 doesn't have an automatic RX IQ balance correction, so that API is removed. The auto-DC offset correction was calling into the manual DC offset correction code, which means auto-DC offset correction was never enabled for N320.
* cmake: tests: Add build-python path to PYTHONPATHMartin Braun2021-09-081-2/+5
| | | | | | | | | | | | | | | | This is more of an expressive change than a functional change; Python seems to add this path to the PYTHONPATH anyway, at least for some systems. We neverless make this change because: - It's more explicit/expressive. When tests are run, the PYTHONPATH env variable is printed, and it now contains this path where it should be, right at the front. People reading the ctest/python.unittest output now get told explicitly which path we mean. - This guarantees that this path is added, even if Python/unittest should behave differently on other systems or versions. To clarify: When running unit tests, we want to run the Python code from build/python, not the installed version. The latter may not yet exist, and if it does, it's not the version we are editing.
* examples: Show how to use in-tree Verilog headerWade Fife2021-09-081-0/+17
| | | | | Adds example showing how to `include an in-tree Verilog header file in the rfnoc_block_gain example.
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-088-16/+8
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* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-083-6/+11
| | | | | | | | | | | | | | | | | This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH
* x300: Fix MAX_RATE_1GIGE valueMartin Braun2021-09-071-1/+1
| | | | It held the same value as MAX_RATE_10GIGE due to a typo.
* ci: Device wait to redlock scope for Vivado closeSteven Koo2021-09-071-2/+2
| | | | | | | | Sometimes Vivado gets reopened too fast causing port in use errors. This moves the device reboot wait into the redlock scope to give some time for Vivado to close before the next agent tries to get the lock. Signed-off-by: Steven Koo <steven.koo@ni.com>
* x4xx_bist: use get_mpm_client in gpio bistGrant Meyerhoff2021-09-021-19/+18
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* mpmd: Add discoverable feature for trig i/o modeGrant Meyerhoff2021-09-026-2/+105
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* tests: Fix check in link_testMartin Braun2021-08-311-2/+2
| | | | | | | | The test_recv_get_release test should be checking received packets had the same content as they did on send(), but was instead assigning to the received buffer. Shoutouts to GitHub user johnwstanford for pointing out the issue.
* uhd: transport: Avoid exceptions in disconnect_receiver()Aaron Rossetto2021-08-311-10/+10
| | | | | | | | | | | | | | | | | | | | inline_io_service::disconnect_receiver() uses the recv_link_if parameter as a key into the _recv_tbl map. In some error cases, notably when an underlying link timeout occurs when setting up a transport, that key may not exist in the table. Attempting to index the table by that non-existent key causes an std::out_of_range exception to be thrown. However, in the aforementioned error case, disconnect_receiver() is called as part of a destructor of an object that is in one of the stack frames being unwound as the timeout exception is in flight. Throwing an exception while one is in flight ultimately causes the C++ runtime to terminate the process. (Generally, throwing an exception in a destructor, unless caught within the destructor, is considered a bad practice for this very reason.) This PR modifies disconnect_receiver() to check for the existence of the entry in the map and bypass the access if it is not present, thus preventing the exception from being thrown in this function which is invoked from another object's destructor.
* rfnoc: ddc: Improve unit tests and documentationMartin Braun2021-08-302-5/+26
| | | | | | | The previous commit fixed a bug in the DUC, where get_frequency_range() reported incorrect values. The DDC did not have this bug, but we port the updates to the unit tests and the documentation from the DUC to the DDC for consistency's sake.
* rfnoc: duc: Fix frequency range for DUC blockMartin Braun2021-08-304-13/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tuning range of the DUC depends on the output sample rate (which is larger), but it was using the input sample rate. This was causing a bug where for Tx, the DSP tuning range was limited when using multi_usrp API, and thus would not allow to DSP-tune beyond the current sampling rate. In this patch, we also re-use the existing calculation of the sampling rate, and harmonize that code between duc_block_control and ddc_block_control. Consider the following Python REPL code: >>> import uhd >>> U = uhd.usrp.MultiUSRP('type=x300') >>> U.set_rx_rate(10e6) >>> U.set_tx_rate(10e6) >>> # Creating a streaming is required, or the input rate will not be >>> # set: >>> S = U.get_tx_stream(uhd.usrp.StreamArgs("fc32", "sc16")) >>> treq = uhd.types.TuneRequest(1e9) >>> treq.rf_freq = 1e9 >>> treq.dsp_freq = 50e6 >>> treq.dsp_freq_policy = uhd.types.TuneRequestPolicy.manual >>> treq.rf_freq_policy = uhd.types.TuneRequestPolicy.manual >>> tres = U.set_rx_freq(treq, 0) >>> print(str(tres)) Tune Result: Target RF Freq: 1000.000000 (MHz) Actual RF Freq: 1000.000000 (MHz) Target DSP Freq: 50.000000 (MHz) Actual DSP Freq: 5.000000 (MHz) >>> # Note the last two lines: The *target* DSP freq was already clipped >>> # to 5 MHz. These lines show 50.0 MHz when this patch is applied. This bugfix is accompanied some related changes: - The unit test is amended to verify the behaviour - The API documentation is amended with details on its behaviour
* python: Add new method bindings to noc_block_baseAaron Rossetto2021-08-301-0/+8
| | | | | This commit adds `get_src_epid()` and `get_port_num()` method bindings to the Python bindings for `noc_block_base`.
* examples: Add x400/x410 target to RFNoC exampleWade Fife2021-08-301-0/+3
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* fpga: Set default part for sim in setupenv.shWade Fife2021-08-306-5/+24
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* cmake: Add check for libatomic linking requirementMartin Braun2021-08-272-0/+95
| | | | | | | | | | Some archs require linking against libatomic, others don't. We add some CMake code that checks for libatomic.so requirement if: - We are not on MSVC, AND - Compiling std::atomics code would cause a linker error. We then check for the existence of libatomic.so, and fail if we can't find it.
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
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* mpm: x4xx: update mboard_max_revAndrew Lynch2021-08-251-1/+1
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* MPM: add X410 support for 250e6 master clock rateMichael Dickens2021-08-241-0/+1
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* uhd: Remove Boost version checks for Boost 1.61Martin Braun2021-08-241-19/+4
| | | | | UHD requires Boost 1.65, so checks for Boost 1.61 will always be satisfied.
* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-08-241-31/+54
| | | | | | | | | The script was previously only Python 2 compatible. Python 2 support is now removed, so we don't maintain backwards compatibility with Python 2. This also fixes all linter warnings.
* ci: Add Fedora 34 and remove Fedora 32Steven Koo2021-08-232-3/+3
| | | | | | Fedora 34 has been released and Fedora 32 is EOL Signed-off-by: Steven Koo <steven.koo@ni.com>
* images: Update manifestmichael-west2021-08-201-8/+8
| | | | | | Update to use FPGA images with recent fixes. Signed-off-by: michael-west <michael.west@ettus.com>
* cmake: remove duplicate entry in LIBUHD_PYTHON_GEN_SOURCEMichael Dickens2021-08-201-5/+0
| | | | Closes: https://github.com/EttusResearch/uhd/issues/478
* tests: Add recv(0) case to rx_streamer_testAaron Rossetto2021-08-201-0/+39
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* uhd: streamer: Restore original recv(0) semanticsAaron Rossetto2021-08-201-0/+32
| | | | | | | | | A recv() of zero samples on an RX stream should return immediately (i.e., without respect to the timeout and regardless of the availability of samples), surfacing any stream error conditions via metadata. This convention was broken in a2f10ee9, causing a recv() of zero samples to wait for the entire timeout period and then return ERROR_CODE_TIMEOUT if no samples are available. This commit restores the desired semantics.
* X300: Initialize struct variable before using itMartin Anderseck2021-08-201-1/+1
| | | | | | | In x300_eth_mgr.cpp the variable init is created but not initialized. Only some of the variables within the struct are then set before init is assigned to a different variable. Initialize the variable to prevent unexpected values.
* lib: transport: Mark typecast as intendedMartin Anderseck2021-08-171-1/+2
| | | | | Remove warning about potential data loss in VS due to typecast by marking it as intended.
* lib: transport: Initialize _hshake_args_serverMartin Anderseck2021-08-171-1/+1
| | | | | Initialize _hshake_args_server to safely use this struct and its contents in line 70.
* B200: Fix overflow handlingmichael-west2021-08-162-18/+13
| | | | | | | - Use FPGA images with fixed sc12 converter. - Properly flush channels and restart streaming in the case of an overrun. Signed-off-by: michael-west <michael.west@ettus.com>
* n3xx: Add support for rev 10michael-west2021-08-161-1/+1
| | | | | | No hardware interface change, so just bumping max revision. Signed-off-by: michael-west <michael.west@ettus.com>
* N320: Reduce PLL lock timemichael-west2021-08-161-5/+5
| | | | | | | - Reduce PLL1 DLD lock count to 4,000 (0xFA0), or 100ms - Change loop to check for lock every 10ms Signed-off-by: michael-west <michael.west@ettus.com>
* mpm: Expose motherboard regs for debuggingSam O'Brien2021-08-131-0/+9
| | | | | | | | | There currently isn't a way to access the motherboard register using MPM (the ones defined in x4xx_global_regs). This commit adds a simple interface to peek and poke them which is very similar to the current interface for the daughter board registers. Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
| | | | | | | Modified to send 2 packets back to back at each packet size to test output during sequential input packets. Also fixed whitespace. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
| | | | | | | Added delay to error packets so overrun error is back in-band. Avoids dropping good data packets in the case of an overrun. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
| | | | | | | | | Re-wrote converter to remove clock cycle delay on i_tready when handling residual output and fixed improper handling of tlast during residual data processing. Resolves some USB overflow issues when using sc12 data type on B200 devices. Signed-off-by: michael-west <michael.west@ettus.com>
* lib: rfnoc: Make implicit typecasts explicitMartin Anderseck2021-08-101-4/+5
| | | | | | Fix implicit typecasts that could potentially lose data. Doing this to show that these typecasts are done on purpose (and to resolve warnings from VS).
* lib: rfnoc: Change enum node_type to enum classMartin Anderseck2021-08-101-23/+25
| | | | | | Fix the "Enum.3: Prefer class enums over "plain" enums" warning for the node_type enum and update the calls to the enumerators as proposed by the C++ Core Guidelines.
* ci: rebuild docker images weeklySteven Koo2021-08-091-0/+14
| | | | Signed-off-by: Steven Koo <steven.koo@ni.com>
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were some rare corner cases where the EOB could get lost in the DUC due to the dds_timed logic not always passing it through as it should. This resulted in an underflow error message at the end of transmission. This commit also fixes an issue where part of the last packet used a frequency shift of 0 instead of the requested frequency shift, and an issue where the first few samples of a burst used the wrong frequency shift value. Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only. The TUSER port is built into the IP but was disabled. It is now enabled and set to 1 bit wide. This has a very small effect on resource usage and can be left unconnected when not needed. The dds_freq_tune block was shared by the DUC and DDC. To avoid affecting the DDC, a new version, dds_freq_tune_duc, is being added for the DUC to use that has the necessary fixes. The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP. This IP has the undesirable behavior that new inputs must be provided to push previous outputs through the IP. This wrapper hides that complexity by adding some logic to ensure all data gets pushed through automatically. This logic uses the TUSER port on the IP. Finally, a testbench for dds_timed was added.
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-085-0/+546
| | | | | | | | | | | | PkgComplex adds functions for doing complex arithmetic in SystemVerilog simulation. PkgMath provides mathematical operations and constants that aren't built into SystemVerilog, such as a constant for pi and the function round(). PkgRandom adds randomization functions beyond what standard Verilog supports but that don't require any special licenses or simulators.
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