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* mpm: Fix various Pylint issuesMartin Braun2020-07-095-13/+9
| | | | | | | | No functional changes. Fixes for things that PyLint complains about, but are safe to change anyway, as well as a minor improvement to a docstring that referenced non-existant args. This touches files that are mpm.conf-related.
* cores: Remove shutdown function from spi_core_3000Martin Braun2020-07-082-21/+0
| | | | | | | | This effectively reverts 0433e74. The set_shutdown() and get_shutdown() API calls do not have a counterpart in simple_spi_core.v, which is typically the HDL endpoint for this core driver, and thus could write to a non-existent register. They are also never used in UHD, nor are they part of the spi_iface interface.
* e3xx: Remove superfluous commentsMartin Braun2020-07-081-11/+0
| | | | This removes some comment that include code that still gets executed.
* meta-ettus: remove io_type.hppSteven Koo2020-07-082-66/+0
| | | | | | | io_type's implementation was removed when host/lib/depricated.cpp was removed. This commit also removes the hpp and installation. Signed-off-by: Steven Koo <steven.koo@ni.com>
* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
| | | | Unused CHDR port was not being drained of discovery packets.
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3014-0/+3340
| | | | | | | | | | | | | | | | | | The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.
* rfnoc: Add unit test for Log Power RFNoC blockAaron Rossetto2020-06-292-0/+85
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* rfnoc: Add Log Power RFNoC block supportAaron Rossetto2020-06-295-0/+88
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* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-297-0/+1062
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* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
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* python: Add window RFNoC block controller bindingsAaron Rossetto2020-06-293-1/+25
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* rfnoc: Add unit test for Window RFNoC blockAaron Rossetto2020-06-292-0/+252
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* rfnoc: Add window RFNoC block controllerAaron Rossetto2020-06-295-0/+220
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* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-299-0/+1510
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* fpga: tools: Highlight suppressible errors from vlintWade Fife2020-06-291-1/+1
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* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
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* CHDR: support multiple CHDR widthsAndrew Lynch2020-06-268-28/+192
| | | | | Support management payloads on busses over 64 bits Automatically set CHDR width for mpmd_link_if_ctrl_udp
* uhd: improved handling of empty serial number hintsMatthew Crymble2020-06-262-0/+5
| | | | | This allows device::find() calls to proceed even when encountering an empty/invalid serial number or serial number device argument hint.
* cmake: tests: Fix CMake warning introduced by QEMU unittest optionJoerg Hofrichter2020-06-261-1/+1
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* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
| | | | | | Contains a fix for the AXI4LITE_ASSIGN macro, and adds AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and AXI4LITE_DEBUG_ASSIGN macros.
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-2520-78/+4195
| | | | | | | | | | | | | | | | | | | Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi
* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
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* fixup! uhd: Add discoverable_features APILane Kolbly2020-06-251-1/+4
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* uhd: Implement discoverable_features for radio_controlLane Kolbly2020-06-252-2/+6
| | | | | radio_control doesn't implement any discoverable_features in particular, but this gives it the API to do so.
* uhd: Create discoverable feature registry implementationLane Kolbly2020-06-257-36/+113
| | | | | | Classes which want to implement discoverable_feature can simply inherit from this registry and get access to an ergonomic map-backed registry of features.
* uhd: Add discoverable_features APILane Kolbly2020-06-256-0/+227
| | | | | | | | The "discoverable features" API handles how clients access the myriad features we offer, without simply adding a million has_FOO and do_FOO methods to radio_control and multi_usrp. discoverable_features allows clients to query the existance of, enumerate, and ultimately they get (by enum or by type) an object which implements their wanted feature.
* cmake: tests: Added option to use QEMU for running unittestsJoerg Hofrichter2020-06-252-1/+33
| | | | | This is useful when cross-compiling UHD for other architectures like arm or aarch64.
* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-246-1/+1099
| | | | | | | | | | | | | | | | | (1) Synthesizable AxiLiteIf (2) Simulation model for AxiLite contains an AxiLiteTransaction class and an AxiLiteBfm class. Important Methods a. wr - performs non-blocking write and checks for expected response b. wr_block - performs a blocking write and provides response c. rd - performs a non-blocking read and checks for expected response d. rd_block - persforms a blocking read and provides response The model allows parallel execution of reads and writes, but enforces rd and write ordering when using the above methods. When transactions are posted directly, ordering is not guaranteed, and reads and writes are put on the interface immediately.
* fpga: lib: Pipeline and add clken to ip_hdr_checksumAndrew Moch2020-06-244-66/+51
| | | | | | | Adds LATENCY parameter to control the ammount of pieplineing. Adds a clock enable to control the advance of the pipeline. Used in xport when calculating new UDP headers for CHDR traffic.
* test: Add verify-flatbuffer testLars Amsel2020-06-232-0/+34
| | | | | | This runs update_fbs.py --verify as a unit test, and fail accordingly. The test passes if git executable is not found or the schema files are not within a git repo, because both are not a dependency of UHD.
* test: Use git hashes to verify flatbuffers schemaLars Amsel2020-06-231-55/+78
| | | | | | | | | | | | Each version of flatbuffers (might) generate different header files for the same schema file. Therefore we cannot compare the content of the generated headers to detect changes in the schema that are not accompanied by a change in the generated header. To have at least a minimal check that the schema matches the generated header we compare the git hashes of both. We will not allow to change the schema without changing the header and vice versa. This condition is checked by a unit test.
* cal: change default extension of calibration filesLars Amsel2020-06-235-16/+30
| | | | | | | | | Flatbuffers offers an option to set the default extension for binary files. Our calibration files have the extension .cal. Set the extension in all schema files to ease conversion between binary and text representation of calibration files. Updated documentation accordingly.
* mpmd: Increase default long timeout to 30 secondsSteve Czabaniuk2020-06-221-2/+2
| | | | | Note: timeouts were occurring on n310 due to an increase in daughterboard re-initialization time.
* utils: update_fbs.py: Minor refactor, fix path bugMartin Braun2020-06-221-9/+15
| | | | | | | - The UHD auto-detection was broken. Now it can find UHD in the same directory. - The main() function was split into main() and run(), which would allow loading this module and calling run() as it's own function.
* utils: Make uhd_images_downloader raise warning for invalid pathsSteve Czabaniuk2020-06-221-11/+21
| | | | | This makes the utility warn the user when they pass a path argument that is invalid; the utility falls back to defaults if this occurs.
* multi_usrp: Assert that edge_lists are non-empty before accessingSteve Czabaniuk2020-06-221-0/+2
| | | | | The edge_list for a given rx/tx chain should never be empty so this explicitly performs that check, which prevents a potential bad access.
* fpga: tools: Fix ModelSim return statusWade Fife2020-06-182-5/+12
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* rfnoc: Update port format in block YAMLWade Fife2020-06-189-22/+22
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* rfnoc: Add makefile_srcs to block YAMLWade Fife2020-06-185-0/+5
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* utils: Support expressions for num_ports in block defsAaron Rossetto2020-06-181-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows the RFNoC image builder utility to support block definition .yml files where the num_ports values are numerical expressions using values sourced from the parameters section when the block is used in an RFNoC image. An example of such an expression for num_ports is the split stream block, where the number of output ports is defined as the product of the NUM_PORTS and NUM_BRANCHES parameters: data: fpga_iface: axis_chdr clk_domain: rfnoc_chdr inputs: in: num_ports: NUM_PORTS outputs: out: num_ports: NUM_PORTS*NUM_BRANCHES In an RFNoC image definition .yml file, these parameters can be specified when a split stream block is instantiated in an image: split0: block_desc: 'split_stream.yml' parameters: NUM_PORTS: 2 NUM_BRANCHES: 3 Thus, the split0 instance of the split stream block is configured with 2 input ports and 6 output ports (2*3 from NUM_PORTS*NUM_BRANCHES). When the RFNoC image builder runs and encounters a block instantiation where that block has a non-integer string in the num_ports key of its block definition, it performs a textual replacement of the identifiers in the string with the corresponding values from the parameters section of the block's instantiation. If no such parameter corresponding to the identifier exists, the block definition file's parameters section is consulted for a default value for the parameter. If no such parameter can be found in either of these locations, the identifier is left unchanged in place. After the text substitution step, the expression is evaluated using Python's expression evaluator. The expression should evaluate to an integer value, which is then used as the num_ports value. If the expression does not evaluate to an integer, or fails to evaluate, an error will be reported.
* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-1820-389/+572
| | | | | | | | This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and chdr_stream_endpoint blocks so that wider CHDR widths are properly supported. It also updates PkgChdrBfm to able to properly test these blocks. The testbenches have been updated to test both 64 and 512-bit widths.
* python: Add FFT RFNoC block controller bindingsAaron Rossetto2020-06-183-0/+49
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* tests: Add unit test for FFT RFNoC blockAaron Rossetto2020-06-182-0/+191
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* rfnoc: Augment FFT RFNoC block controllerAaron Rossetto2020-06-183-56/+250
| | | | | | | This commit augments the existing FFT RFNoC block controller with C++ functions through which the block can be configured, as well as adding range checking to the various properties that sit atop the FFT RFNoC block registers.
* cal: Add automated port switchLars Amsel2020-06-174-20/+150
| | | | | | | | | | | | | | | | | Current implementation needed manual interaction to calibrate each antenna. More sophisticated setups are able to switch between channels and antennas programmatically. This commit introduces a base class that handle the switch behaviour. The previous implementation moved to a ManualSwitch class which is the default switch. Without any options the previous flow remains unchanged. A new class is able to handle NI switch models. The switch port can be given via options parameter (comA is default). The channels are connected in ascending order. The user has to ensure that the cable setup matches the order given for channels and antennas. Co-authored-by: Martin Braun <martin.braun@ettus.com>
* cmake: Fix warning finding libusbMartin Braun2020-06-172-3/+3
| | | | | | | | | | UHD has a custom file to find libusb. This fixes a warning coming from that file caused by the fact that we're looking for a package called LIBUSB, but the file was called FindUSB1 (i.e., we're expecting a package name of USB1). Common CMake calls were also moved to lowercase for CMake coding guidelines consistency.
* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
| | | | | | | | | The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This commit adds a second spi core with capability to transfer up to 64 bits while keeping the same amount of resources when using generic setting MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the edges of sclk. The register stages were not aligned in the existing version.
* fpga: tools: remove temporary Xilinx directories for BD recreationMax Köhler2020-06-151-10/+13
| | | | | | | During recreation of block diagrams any RTL modules will be kept in hidden directories within the build directory. Updates of the RTL sources might not be taken into account. Solution is to remove Xilinx's hidden project directories before calling vivado.
* cal: Add switch documentationLars Amsel2020-06-151-2/+24
| | | | | | | | | Add chapter to explain usage of supported switch classes which handle connection of DUT and measurement devices. Documentation is done for ManualSwitch (default) and NI switch for devices that can be used by the niswitch Python package. Co-authored-by: Martin Braun <martin.braun@ettus.com>
* tests: Add infrastructure to run Python unit testsMartin Braun2020-06-153-0/+49
| | | | | | | | | | | | | | | | - Add UHD_ADD_PYTEST() CMake macro - Add CMake code to tests/CMakeLists.txt to auto-run all registered Python unit tests - Add a token unit test (it replicates parts of ranges_test.cpp) The way Python-based unit tests are implemented in UHD is that they can import uhd, and then operate on the module as usual. Writing unit tests in Python instead of C++ can have multiple advantages: - If they test PyBind-wrapped C++ code, they can test both the binding and the underlying C++ code at once - Writing unit tests in Python may be more concise
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