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* docs: zbx: address review observations in docsHumberto Jimenez2021-06-221-2/+2
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* docs: usrp_x4xx: address review observations in docsHumberto Jimenez2021-06-223-70/+157
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* mpm: restore rfdc nco frequency after setting sync sourceGrant Meyerhoff2021-06-222-0/+31
| | | | After setting sync sources, the RFDCs get reset, we need to restore the previously set frequencies so that the device continues to transmit/receive at the requested frequency
* x3xx: Improve image loaderMartin Braun2021-06-221-27/+44
| | | | | | | - When specifying a file path, no longer infer the FPGA type for the logging from the image that is currently loaded. - Use sanitize product names for ni-2974 everywhere were appropriate - Remove some usages of boost::format that weren't doing anything useful
* usrp2: Use explicit template type for std::min<T>StefanBruens2021-06-221-1/+1
| | | | Signed-off-by: Aaron Rossetto <aaron.rossetto@ni.com>
* usrp2: Replace boost::math::iround/math::sign with std::lroundStefanBruens2021-06-221-5/+5
| | | | | | | | | Instead of multiplying zone with the sign repeatedly just make the zone a signed value. See #437, #438 Signed-off-by: Aaron Rossetto <aaron.rossetto@ni.com>
* docs: Fix typosf380cedric2021-06-221-3/+3
| | | | Signed-off-by: Aaron Rossetto <aaron.rossetto@ni.com>
* docs: Fix python3-ruamel.yaml name on RPM based OSf380cedric2021-06-221-2/+2
| | | | | | The package is named python3-ruamel-yaml on RHEL & derivatives. Signed-off-by: Aaron Rossetto <aaron.rossetto@ni.com>
* usrp2: Apply minor cleanups to Boost usage in usrp2Martin Braun2021-06-181-9/+8
| | | | | | | - Inconsistent usage of asio:: or boost::asio:: (now uses the latter consistently) - Removed some usage of boost::format() where it really didn't add any value
* docs: zbx: update cpld source code locationHumberto Jimenez2021-06-181-1/+1
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* docs: usrp_x4xx: apply minor corrections in docsHumberto Jimenez2021-06-181-41/+40
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* uhd: Add missing channel parameter when reading power ref keysLars Amsel2021-06-181-2/+2
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* mpm: tests: Add lib/ to library load pathAaron Rossetto2021-06-181-1/+8
| | | | | Ensure that DYLD_LIBRARY_PATH on OS X or LD_LIBRARY_PATH on Linux platforms is set appropriately before invoking MPM's Python unit tests.
* test: add DPDK option for max streaming rate testsMatthew Crymble2021-06-183-82/+230
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* uhd: Add callback for setting sync_sourcesGrant Meyerhoff2021-06-174-0/+53
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* usrp2: Fix Boost headersMartin Braun2021-06-171-2/+2
| | | | | | | | | On Boost 1.76, this would otherwise fail with an error: [...] .../usrp2_impl.cpp:920:37: error: ‘boost::math’ has not been declared 920 | const int sign = boost::math::sign(new_freq); [...]
* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
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* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-1711-136/+303
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* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-177-3/+212
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* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
| | | | | | | This change allows assertion errors/failures in ModelSim to be detected and causes ModelSim to return a non-zero value when such an assertion error occurs. This allows the return value of ModelSim to be used to determine whether or not the testbench passed.
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
| | | | | | VHDL depends on the compile order. This commit changes the order so that SIM_SRCS are compiled last with ModelSim to avoid issues with dependencies.
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
| | | | | | This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado.
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
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* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
| | | | | This is a list of testbenches that don't work with ModelSim and should be excluded when running run_testbenches.py.
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
| | | | | | | | | | | This adds the MSIM_VIV_COMPLIBDIR environment variable to specify a non-default location for the compilation libraries. This also allows a modelsim.ini other than the one in the ModelSim installation folder to be used. By default, the one in the simulation libraries compilation directory will be used. This can be changed by setting MSIM_MODELSIM_INI to the one you want to use, or set it to an empty string to use the one in the ModelSim installation folder.
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
| | | | | | | | | | | | | | | | Run "make ip" in a separate step for each testbench. This allows some testbenches to work better with ModelSim because it needs IP files that aren't known until after the IP is generated. Make run_testbenches.py more log friendly. Add a -l/--logged option for when the output is being logged. In this case, we don't want to display elapsed time every second. Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell where the output from one testbench ends and another begins. Use the basedir argument as the base directory in which to search for testbenches so that a subset of the repo can be easily specified.
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-172-2/+6
| | | | | Allow building of just the IP by running "make ip" in simulation directories.
* uhd: Update versionAaron Rossetto2021-06-161-1/+1
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* docs: zbx: improve cpld update docsMichael Auchter2021-06-161-7/+5
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* docs: usrp_x4xx: improve mb cpld update docsMichael Auchter2021-06-161-3/+2
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* mpm: install cpld update scripts in runtime dirMichael Auchter2021-06-161-0/+10
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* mpm: x4xx_bist: run spi_flash tests on both DBsMichael Auchter2021-06-151-9/+29
| | | | | By default, run the spi_flash tests on both daughterboards instead of only the first one.
* uhd: x400: Honor ENABLE_X400 component flagAaron Rossetto2021-06-151-9/+14
| | | | Don't add X400-related sources to libuhd if they are not requested.
* images: Update manifestAaron Rossetto2021-06-111-12/+12
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* mpm: max10_cpld_flash_ctrl: only reprogram cpld if necessaryMichael Auchter2021-06-101-0/+8
| | | | | | | When updating the CPLD via the flash method, first read back the CPLD image from flash and compare it with the image to be programmed. If they match, the CPLD is already running the correct image and reprogramming it is not necessary.
* uhd: ci: Add test definition for UHD CIJoerg Hofrichter2021-06-105-2/+449
| | | | | Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes@ni.com>
* uhd: Add support for the USRP X410Lars Amsel2021-06-10185-160/+61559
| | | | | | | | | | | | | | | | Co-authored-by: Lars Amsel <lars.amsel@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Lane Kolbly <lane.kolbly@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Andrew Lynch <andrew.lynch@ni.com> Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>
* images: add X410 series FPGA imagesJoerg Hofrichter2021-06-101-0/+6
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* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
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* fpga: ci: Add build definitions for FPGA CIWade Fife2021-06-107-0/+483
| | | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
| | | | | | | Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
| | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10207-1/+299667
| | | | | | | | | | | | | Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
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* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
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* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
| | | | | | Update rfnoc_image_core.v to take into account the new image_core_name fields and version strings. Add new rfnoc_image_core.vh. Update YAML where needed.
* fpga: Update recommended HDL header guidelineWade Fife2021-06-101-0/+3
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* transport: Set mtu to 9000 for all 10GbE use casesmattprost2021-06-103-8/+8
| | | | | | | | An default MTU value of 9000 gives the devices the most flexibility using 10GbE. Many interfaces and docs have already been updated. This is bringing all devices into alignment with this paradigm. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
| | | | | | | | | | | | | | The script setupenv_base.sh, which is used to setup the development environmnet in the open source toolchain, adds some functions to the shell that are used to interact with vivado. Some of the functions were looking in the wrong argument for the product name. This commit fixes the bug. In addition, supplying an incorrect part name returned a rather opaque error message. This commit also fixes the error handling so that the intended error message is displayed. Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
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