aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* rh: change uio access to utilize with-asMark Meserve2018-11-122-79/+85
|
* mpm: i2c: Open and close i2c file descriptor on every accessAlex Williams2018-11-122-24/+48
| | | | | | This will release the i2c device when it's not in use. If MPM hangs on to the i2c devices, we won't be able to cleanly change FPGA images--The kernel hangs up the process until the refcount drops to zero.
* uhd: add .clang-format fileBrent Stapleton2018-11-121-0/+92
| | | | | | Adding clang-format configuration file. The chosen style is meant to match current UHD coding style, except in certain cases where we have consciously decided to format our code in a particular way.
* images: Add Rhodium CPLD image to manifestAlex Williams2018-11-091-0/+5
|
* docs: n3xx & e320: Add more information on SaltMartin Braun2018-11-082-0/+83
|
* mpm: n3xx_bist: Add QSFP loopback to BIST testsAlex Williams2018-11-071-1/+45
|
* mpm: Add basic driver for QSFP board's retimerAlex Williams2018-11-074-0/+142
|
* mpm: Add convenience function to pull i2c bus from device treeAlex Williams2018-11-072-0/+37
| | | | | This function grabs the i2c character device path from the OF_NAME property. That property must be unique in the device tree!
* rh: initialize switchesMark Meserve2018-11-071-3/+10
|
* docs: x300: Add section on motherboard clockingMartin Braun2018-11-071-0/+50
|
* x300: Remove 120 MHz optionMartin Braun2018-11-072-3/+1
| | | | | None of our FPGA images support a 120 MHz master clock rate, so the UHD code should match that.
* mpm: rh: Add MAX 10 update scriptAlex Williams2018-11-071-0/+165
|
* images: Add Rh images to the image_package_mapping scriptMartin Braun2018-11-071-0/+24
| | | | This enables a default package for Rhodium images.
* rh: adjust tx lo gain tableMark Meserve2018-11-052-7/+12
| | | | - Improves performance for frequencies greater than 3.5 GHz
* rh: add lo distribution supportMark Meserve2018-11-057-4/+306
| | | | | | | | | - This is a combination of 5 commits. - rh: add lo distribution board gpio expander - rh: add lo distribution mpm functions - rh: add code to conditionally initialize lo distribution - rh: change empty i2c device from exception to assertion - rh: add lo distribution board control
* rh: fix handling of spur_dodging argMark Meserve2018-11-013-7/+30
|
* uhd: Changes to traffic counter register namesCiro Nishiguchi2018-10-312-78/+62
| | | | | | This makes the noc traffic counter register actually reflect the registers in the FPGA. The FPGA register names were changed prior to merging to master, and the ready count registers were removed.
* tests: device3_test: add graph impl testTrung Tran2018-10-317-59/+295
|
* rh: disable lmk test outputMark Meserve2018-10-301-1/+1
| | | | - Improves spur performance
* rh: Phase DAC configuration clean-upHumberto Jimenez2018-10-301-6/+4
| | | | | | | | | | | | | | | | | | | | | - Confirmed the Phase DAC to be initialized at mid-scale. - Confirmed the Phase DAC step resolution for fine clock shifting. The clock synchronization algorithm relies on the Phase DAC to fine shift the sampling clocks on each daughterboard. Only a certain number of DAC codes are required for the actual clock adjustment, thus a different range of codes may be chosen by initializing the Phase DAC with a given value. With the selected range, one may measure the Phase DAC's linearity and step resolution, which defines how many steps are required when performing the fine shifting of the clocks. After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and 75%; it was found that the clock distribution PLL locks relatively faster when using mid-scale (2^15). By testing the Phase DAC's linearity, it was confirmed that the circuit resolution is 1.11 ps per code.
* rh: Deterministic latency optimization in JESD204BHumberto Jimenez2018-10-301-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Optimized JESD204B RX/TX links' latency. - Made JESD latency constant across supported frequencies. - Checking RX SYSREF capture in the FPGA deframer block. The JESD204B standard can be linked in such a way to produce a repeatable, deterministic delay from the framer to deframer. This is accomplished by setting up a LMFC (local multiframe clock) in both devices. The LMFCs are reset whenever a SYSREF edge is captured by the framer and deframer. Therefore, it is simple to control the LMFC rising edges in each device by implementing variable delay elements on the SYSREF pulses to the framer and deframer. Latency across the JESD204B TX/RX links should remain constant and deterministic across the supported sampling_clock_rate values. By testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with different delay values in the FPGA, one may decrease the latency and provide enough setup and hold margin for the data to be transfered through each JESD link. It was found that a different set of SYSREF delay values are required for sampling_clock_rate = 400 MSPS to match the latency of the other supported rates.
* debian: Update control files for .deb filesMartin Braun2018-10-294-21/+29
| | | | | | | | | - Better alignement with public Debian files. - Move to a different package name: libuhd003.so -> libuhd3.13.0.so This allows to install multiple packages in parallel for better ABI compatibility by third-party dependees. The new package replaces the old one. - Remove .shlibs file
* cmake: Change SOVERSION and VERSION for the library filesMartin Braun2018-10-292-2/+9
| | | | | | The SOVERSION will now match the ABI string, and the VERSION matches the full UHD version. This will allow easier parallel installation of multiple versions of UHD.
* cores:rx_frontend_core_3000: fix real modeGwenhael Goavec-Merou2018-10-291-0/+2
|
* python: Add missing constructors of time_spec_tPiotr Krysik2018-10-251-0/+3
| | | | | | Currently Python interface of time_spec_t exposes only constructor with 'double' parameter. Other constructors are also important as they provide higher precision. This change adds them to the Python API.
* manifest: FPGA bug fixesBrent Stapleton2018-10-252-9/+11
| | | | | | | | | | | | | | Updating FPGA images for the following devices with the following bug fixes. No compat number bumps included in the changes. Also updating the submodule pointer. X3xx, N3xx, E3xx: - DDS flushing fix - Fix sequence number clearing B2xx: - Async reset from misc registers - Redistributed buffering in radio and xport
* rh: add support for rhodium devicesMark Meserve2018-10-2526-4/+6147
| | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ni.com>
* nijesdcore: add PRBS-31 testingMark Meserve2018-10-251-0/+37
|
* nijesdcore: add eyescan utilityMark Meserve2018-10-253-4/+860
|
* nijesdcore: add variable configuration supportMark Meserve2018-10-254-30/+50
|
* mpm: tools: Added Rhodium ID to db-id utilityDerek Kozel2018-10-251-1/+3
|
* Test: Add unit test for eeprom_utilsmichael-west2018-10-254-2/+63
|
* X300: Prevent duplicate MAC and IP addresses from being programmed in MBMichael West2018-10-252-2/+104
| | | | EEPROM
* X300: Add recovery for duplicate IP addresses in EEPROMMichael West2018-10-252-19/+13
| | | | | - Limit initialization to ZPU communication if recover_mb_eeprom=1 is set in device args.
* mpm: e320: n3xx: Factor BIST code to common moduleMartin Braun2018-10-243-1070/+786
|
* block_ctrl_base: add UHD_SAFE_CALL to destructorTrung Tran2018-10-241-13/+15
| | | | | This will stop the exception throw during destructor of E310 where new FPGA image(idle image) is load.
* n3xx: output exception string on boot init failureMark Meserve2018-10-241-1/+1
|
* cmake: Bump CMake minimum version to 2.8.12Martin Braun2018-10-241-2/+2
| | | | | | This enables some interesting features we can now use in UHD, such as: - target_compile_options - add_compile_options
* UHD: Fix RX streamer SOB and EOB handlingMichael West2018-10-241-2/+9
|
* mpm: Add lock_guard() functionMartin Braun2018-10-231-0/+22
| | | | | This allows sharing mutexes between C++ and Python, and uses the with statement to provide a locked-out context.
* multi_usrp: Improve documentation for set_{time,clock,sync}_sourceMartin Braun2018-10-221-14/+95
| | | | | - Added note on bad-value-handling (throws uhd::value_error) - Added notes on what happens on re-init
* docs: n3xx: Improve sections on clock/time referencesMartin Braun2018-10-221-9/+22
| | | | | | - Added more detail on how to use White Rabbit - Highlight the options with external clock source (with or without external time source)
* mpm:n3xx: improve set_time_source,set_clock_sourceTrung Tran2018-10-221-50/+88
| | | | | | Add coercing behavior to set_time_source and set_clock_source to a valid sync source. Also, skip set_sync_source if device already set to the corresponding one.
* mpm: i2c: Add vector-based transfer functionAlex Williams2018-10-193-0/+41
| | | | This could lead to a less-restricted implementation for use in Python.
* mpm: Add i2c APIs for simple transfersAlex Williams2018-10-1911-0/+496
|
* mg: adding skip_rfic argumentTrung Tran2018-10-182-3/+6
| | | | | | This change to add skip_rfic as an device argument. skip_rfic should be only used in ref_clock bist tests to bring down the test time.
* e320_bist: print extra output ref_clock testsTrung Tran2018-10-181-3/+6
|
* n3xx_bist: add ref_clock bistTrung Tran2018-10-181-45/+107
|
* mpm: identify sysfs gpios more genericallyMark Meserve2018-10-184-22/+59
| | | | | - Allow generic path names to be given for each search parameter instead of only checking the label
* uhd: Add dual measurements to benchmark_streamerCiro Nishiguchi2018-10-181-113/+314
| | | | | Add options to run benchmark_streamer with multiple streamers running concurrently on separate threads.
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-01 18:04:32 +0000