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* docs: Update E320 docsMartin Braun2022-03-281-1/+15
| | | | | - Clarify purpose of 'enclosure' flag - Add section on clock and time sync, which the E31x section already has
* mpm: e3xx: Fix get_sync_sources() APIMartin Braun2022-03-283-2/+30
| | | | | | | | | | | | | | get_sync_sources() was not implemented for E31x and E320. Because UHD assumes this exists, calling this would cause an error like this: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=e3xx") >>> U.get_sync_sources(0) Traceback (most recent call last): File "<input>", line 1, in <module> U.get_sync_sources(0) RuntimeError: rpc::timeout: Timeout of 2000ms while calling RPC function 'get_sync_sources'
* mpm: PeriphManagerBase: List all sync-related methodsMartin Braun2022-03-281-0/+59
| | | | | | | | | | All PeriphManagerBase childs need to implement - get_{clock,time,sync}_source() - get_{clock,time,sync}_sources() - set_{clock,time,sync}_source() So we populate PeriphManagerBase with defaults for all of those.
* mpm: Make default clock/time source values state-lessMartin Braun2022-03-284-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the default clock/time source is whatever the user configured in the last session. This fixes the scenario were you have any MPM device and do this: $ benchmark_rate --args $args,clock_source=external But whoops! You forgot to attach an external 10 MHz. PLL lock fails, nothing works. No worries, you run it again: $ benchmark_rate --args $args With the previous behaviour, this would retain the setting to 'external', because there's nothing to overwrite it. You would need to append `clock_source=internal` to get a working device again. Calling multi_usrp::set_clock_source("internal"), or a similar API call, might not be sufficient because the PLL lock failure might crash the program before updating the clock source is possible. The problem with this is twofold: - All non-MPM devices behave differently, i.e., they have a fixed default ('internal') which is always applied if no other option is given. This is an internal inconsistency. - Some applications (like gr-uhd's GRC bindings) simply don't set a clock/time source when selecting a "default", or they try and update the clock/time source using the API calls. Therefore, we align the behaviour of MPM devices with the other devices, and fall back to an internal source if nothing else is provided.
* mpm: e3xx: Simplify code referring to self.dboardsMartin Braun2022-03-282-42/+24
| | | | | | | | | | | | The E31x and E320 devices have one virtual daughterboard, and it is always present. This is different from N3xx, which is where the MPM code for these devices is based upon. During the E3xx initialization, we make sure that our single "daughterboard" exists and is responsive. That means we can remove some code that tests for the availability and number of daughterboards, which we need on N3xx (which works with zero, one, or two daughterboards). This also allows us some minor deduplication of code.
* fixup! uhd: add support for max10 variantsVirendra Kakade2022-03-281-2/+4
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* tests: use new args for x410 streaming testsVirendra Kakade2022-03-281-0/+6
| | | | | | | | Use new benchmark_rate args "--multi_streamer" and "--priority" for X410 streaming tests. This gets the best performance from the streaming host machine. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* fpga: n3xx: Fix clock frequency commentsWade Fife2022-03-261-2/+2
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* docs: x4xx: Remove redundant GPIO sectionLane Kolbly2022-03-251-4/+0
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* docs: rfnoc: Add doxygen tag for missing parameterMartin Braun2022-03-251-0/+1
| | | | This adds a doxygen tag for the `chan` parameter in fir_filter_block_control::set_coefficients().
* tools: Fix control packet byte enable in CHDR dissectorWade Fife2022-03-251-1/+1
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* test: x410: Add GPIO tests to X410 devtestLane Kolbly2022-03-233-6/+84
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* host: devtest: Allow getting mgmt_addr in testsLane Kolbly2022-03-231-1/+1
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* tools: Add general purpose tool for USRP configurationLars Amsel2022-03-2322-10/+510
| | | | | | | | Over the years the UHD code base got a whole bunch of tools to control and configure devices. This is an attempt to unify these tools into one. Co-authored-by: Alexander Weber <alexander.weber@ni.com>
* rfnoc: fir filter: Add support for multiple channels to block controllerJonathon Pendlum2022-03-233-133/+218
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* mpm: speed up reading gps mboard sensorsDavid Raeman2022-03-231-13/+9
| | | | | | This commit uses a more performant buffered I/O approach for reading the gpsd socket. Previously, querying a gps mboard sensor on an mpm radio would take 300-500ms due to the loop reading one byte at a time.
* images: Update manifest and compat number for X410Humberto Jimenez2022-03-232-2/+2
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* test: add support for new benchmark_rate argsVirendra Kakade2022-03-232-8/+12
| | | | | | | | Add support for the new "priority" and "multi_streamer" benchmark_rate args to run_benchmark_rate.py to enable batch runs of benchmark_rate using those arguments. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
* mpm: n3xx: Recommend reboot USRP after BISTAaron Rossetto2022-03-231-1/+4
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* host: devtest: Add GPIO tests for reading back ATR settingsLane Kolbly2022-03-232-1/+30
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* mpm: x4xx: Remove GPIO classic mode registerLane Kolbly2022-03-231-12/+2
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* host: x410: Emulate GPIO classic ATR mode using new modeLane Kolbly2022-03-233-13/+83
| | | | | | This fixes an issue with setting the active channel source in MPM, and additionally allows opening up the more flexible API in the future without requiring a filesystem update.
* host: x410: Cache GPIO source in mb_controllerLane Kolbly2022-03-233-1/+12
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* Fix handling of discontinuities in power calibration dataLars Amsel2022-03-237-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power that corresponds to a certain gain values depends on the frequency band we are in. At the edges of these bands discontinuities can occur (the gain necessary to achieve the same power value changes non-continuously). The power calibration does a linear interpolation between two neighbor points in the calibration data set to find at best fitting value. We therefore have to make sure that this interpolation does not cross discontinuities. This is a minimal invasive approach. It adds values at discontinuities for the lower and the upper band. The power calibration format uses the frequency for a power to gain mapping as a map key. Therefore two gain to power mappings cannot be stored for the same frequency as it would be needed for the discontinuity. Instead the mapping for the lower band is stored at the discontinuity frequency itself. The mapping for the upper band is stored at the frequency + 1Hz. The calibration will therefore still fail to yield proper results within this sub-Hertz range. The frequency lookup in the power calibration manager now uses round instead of truncation to find the best mapping frequency in the calibration table. With this, searching for neighbor data points now ensures that the data points used belong to the same band (except for the range of (f_discontinuity, f_discontinuity + 1Hz) ). This commit does not solve the issue for calibration data generated with usrp_power_cal.py because the Python interface has no means to detect band edges for the USRP it is calibrating.
* fpga: e31x: Update DRAM IP simulationWade Fife2022-03-231-4/+22
| | | | | Update the simulation to use the renamed IP. Add ModelSim support.
* fpga: e31x: Fix DRAM traffic gen IP nameWade Fife2022-03-231-1/+1
| | | | | Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
* docs: Improve table on 'identification'Martin Braun2022-03-231-8/+8
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* fixup! docs: Update instructions for changing hostnameWade Fife2022-03-231-2/+2
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* docs: Update instructions for changing hostnameWade Fife2022-03-233-12/+12
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* docs: Update sfp port config locationWade Fife2022-03-232-4/+4
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* mpm: Factor out common code between E31x_db and Neon classesMartin Braun2022-03-175-314/+222
| | | | | These classes share a *lot* of common code, due to them both being AD9361-based devices. This code is now factored out into a single file.
* mpm: e3xx: Fix Pylint warnings in periph_mgr classesMartin Braun2022-03-172-14/+11
| | | | | | - Whitespace - Long lines - Superfluous imports
* host: Add power_reference_iface::sptr declarationLane Kolbly2022-03-171-0/+2
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* fpga: ci: Schedule weekly FPGA pipeline runHumberto Jimenez2022-03-161-0/+8
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* fpga: ci: Improve IP build cachingHumberto Jimenez2022-03-151-8/+20
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* fpga: ci: Add stages-based pipelineHumberto Jimenez2022-03-1513-271/+613
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* fpga: ci: Ignore objects in hwtoolsHumberto Jimenez2022-03-151-0/+2
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* fpga: tools: Add CG_400 image to X410 binaries packageHumberto Jimenez2022-03-151-0/+5
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* docs: Update manual for new X410 default targetsWade Fife2022-03-142-14/+18
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* fpga: x400: Add x410_400_128_rfnoc_image_coreWade Fife2022-03-145-3/+1613
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* docs: Fix Doxygen warningsMartin Braun2022-03-142-18/+5
| | | | | | - Removed variables that have been deprecated in newer Doxygen versions - Replaced <speedgrade> with $speedgrade in E310 manual; Doxygen thinks it's an HTML tag.
* python: Add __init__ to uhd.utilsMartin Braun2022-03-141-0/+0
| | | | | | | | | | | | | | | | | Without this, the following code fails: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=x4xx") >>> M = U.get_mpm_client() Traceback (most recent call last): File "<input>", line 1, in <module> M = U.get_mpm_client() File ".../uhd/usrp/multi_usrp.py", line 37, in <lambda> setattr(self, 'get_mpm_client', lambda: _get_mpm_client(token, mb_args)) File ".../uhd/usrp/multi_usrp.py", line 19, in _get_mpm_client from uhd.utils import mpmtools ModuleNotFoundError: No module named 'uhd.utils'
* host: Create meta_range_t::as_monotonicLane Kolbly2022-03-143-1/+62
| | | | | | | | In order to perform certain operations (start/stop/step), meta_range_t objects must be "monotonic", meaning that the subranges composing it are sorted and non-overlapping. This commit creates a method which takes a non-monotonic meta_range_t containing no non-continuous subranges and converts it into a monotonic meta_range_t.
* docs: Fix reference to RFNoC documentationMartin Braun2022-03-141-1/+7
| | | | This fixes links to RFNoC docs in the "Coding to the API" section.
* docs: rdtesting: Remove invalid rate configurationMartin Braun2022-03-141-1/+0
| | | | | Removes an invalid rate configuration for N310 functional FPGA verification tests.
* host: test: Add UHD_UNITTEST_LOG_LEVEL overrideLane Kolbly2022-03-113-21/+55
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* docs: stream_args: Clarify usage of stream_args_t::channelsMartin Braun2022-03-111-15/+23
| | | | | This vector is no longer used with RFNoC devices. We remove references to X300 from the example, and instead use B210 as an example.
* rfnoc: Remove UHD3-API usagesMartin Braun2022-03-112-14/+0
| | | | | | | - rfnoc_replay_samples_from_file still had UHD3-vestiges for selecting block port and ID - The documentation for stream_args_t also included block port and ID examples
* images: Update manifest and compat number for X410Aaron Rossetto2022-03-102-2/+2
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* fpga: rfnoc: Fix PPS edge detectionmichael-west2022-03-091-1/+1
| | | | | | | Make timekeeper module sample rising edge instead of falling edge of PPS signal. Signed-off-by: michael-west <michael.west@ettus.com>
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