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* Merge branch 'fpga_next' into nextJosh Blum2012-07-194-4/+4
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| * e100: tighten timing - less routing on EM_AJosh Blum2012-07-194-4/+4
| | | | | | | | | | There were a few places it was ok to use addr over EM_A. This makes routing sligtly easier for GPMC signals.
* | e100: added extra error message for FPGA not foundJosh Blum2012-07-191-1/+8
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* | Merge branch 'master' into nextJosh Blum2012-07-191-1/+1
|\ \ | | | | | | | | | | | | Conflicts: host/CMakeLists.txt
| * | uhd: updated images url for maint e100 fixJosh Blum2012-07-191-1/+1
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* | | b100/e100: clock source option for pps phase sync abuseJosh Blum2012-07-193-1/+27
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* | | b100: firmware updates for next branch compatabilityJosh Blum2012-07-193-29/+33
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* | | Merge branch 'fpga_next' into nextJosh Blum2012-07-191-1/+8
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| * | u1plus: added sr misc hook for clock syncJosh Blum2012-07-181-1/+8
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* | | docs: added comparative features list at top of eachJosh Blum2012-07-176-9/+65
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* | | e100: remove the test utils, NA anymoreJosh Blum2012-07-175-474/+0
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* | | images: updated images Makefile for E1x0 renameJosh Blum2012-07-171-2/+2
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* | | Merge branch 'fpga_next' into nextJosh Blum2012-07-1713-724/+219
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| * | e100: renamed top level for E100/E110 to E1x0Josh Blum2012-07-176-16/+16
| | | | | | | | | | | | Some minor tweaks to gpmc_to_fifo + timing
| * | E100: squash E100/E110 top level workJosh Blum2012-07-166-531/+84
| | | | | | | | | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPMC. Uses the common core for E100/B100.
| * | gpmc: squashed GPMC FIFO work for E100Josh Blum2012-07-165-162/+93
| | | | | | | | | | | | | | | The control and data slaves are now both implemented as FIFOs. Requires another squash of E100 top level to use.
| * | gpmc: tighter timing constraints and easier to route gpmc to fifoJosh Blum2012-07-162-26/+37
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| * | Merge branch 'master' into nextJosh Blum2012-07-163-43/+6
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* | | | e100: ctrl impl changes for header offsetJosh Blum2012-07-161-2/+2
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* | | | e100: cleanup and make better use of IRQ gpio for control responseJosh Blum2012-07-161-50/+45
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* | | | e100: squashed host code for fifo control/timed commandsJosh Blum2012-07-168-364/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the new b100/e100 common core and FIFO control modules. Subsequent commit will be the compatible FPGA merge. Conflicts: host/lib/usrp/e100/io_impl.cpp
* | | | Merge branch 'master' into nextJosh Blum2012-07-168-49/+21
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| * | | Merge branch 'maint'Josh Blum2012-07-161-1/+4
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| | * | | e100: set vita header offset for previous FPGA changesetJosh Blum2012-07-161-1/+4
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| | * | | Merge branch 'fpga_maint' into maintJosh Blum2012-07-163-43/+6
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| * | \ \ \ Merge branch 'fpga_master'Josh Blum2012-07-163-43/+6
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| | * | | | Merge branch 'maint'Josh Blum2012-07-163-43/+6
| | |\ \ \ \ | | | | |/ / | | | |/| | | | | | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| | | * | | e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-152-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | This effectivly works around bus initial transaction issues.
| | | * | | e100: reverted commit registering in gpmcJosh Blum2012-07-151-38/+1
| | | | | | | | | | | | | | | | | | | | | | | | There is a subtle bus issue that the last changset did not address.
| * | | | | Merge branch 'maint'Josh Blum2012-07-121-1/+1
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| | * | | | n2xx: fix for usrp_n2xx_net_burner addr decode failureJosh Blum2012-07-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the windows network address extractor: The except: continue line could get use stuck in an infinite loop. This fix sets addr to None so the code below it does not execute, and the next node in the chain is tested as expected.
| * | | | | usrp: cache writes to gpio pins (avoids overhead)Josh Blum2012-07-061-1/+7
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| * | | | | Merge branch 'maint'Josh Blum2012-07-061-1/+1
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| | * | | | uhd: docstring typo fix version.hppJosh Blum2012-07-041-1/+1
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| * | | | | lib: FW/FPGA compatibility error prompts user to use regular card/net burner ↵Nicholas Corgan2012-07-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | instead of gui
| * | | | | Merge branch 'fpga_master'Josh Blum2012-07-0213-393/+4134
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* | | | | | uhd: update image fetcher for next branchJosh Blum2012-07-101-1/+1
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* | | | | | uhd: make range_t a lightweight objectJosh Blum2012-07-043-19/+9
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* | | | | | Merge branch 'fpga_next' into nextJosh Blum2012-07-0223-1214/+4958
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| * | | | | B100: squash B100 top level workJosh Blum2012-07-024-406/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPIF. Implements a common core for E100/B100.
| * | | | | gpif: squashed GPIF slave fifo work for B100Josh Blum2012-07-024-414/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The control and data enpoints are now both implemented as FIFOs. Requires another squash of B100 top level to use.
| * | | | | fifo: added module packet_padder36 to fifo/Josh Blum2012-07-022-1/+157
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| * | | | b100: removed unused proto filesJosh Blum2012-06-133-390/+0
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| * | | | fpga: added setting regs based simple_i2c_coreJosh Blum2012-05-302-0/+117
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| * | | | fpga: added some parameterization to settings_fifo_ctrlJosh Blum2012-05-301-3/+6
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| * | | | fpga: added various models from ISEJosh Blum2012-05-307-0/+4011
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* | | | | b100: squashed host code for fifo control/timed commandsJosh Blum2012-07-026-215/+99
| | | | | | | | | | | | | | | | | | | | | | | | | This uses the new b100/e100 common core and FIFO control modules. Subsequent commit will be the compatible FPGA merge.
* | | | | usrp: added fifo_ctrl_excelsior for FIFO control + async msgsJosh Blum2012-07-023-1/+358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fifo_ctrl_excelsior is the host code for dealing with E100/B100 control messages and async messages. It also has the SPI implementation. Timed commands are implemented on top of this code.
* | | | | transport: multi-threaded send_packet_handlerJosh Blum2012-07-021-25/+77
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* | | | | transport: multi-threaded recv_packet_handlerJosh Blum2012-07-021-22/+71
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