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* docs: Add DPDK link detection sectionAaron Rossetto2020-09-031-1/+17
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* dpdk: Improve link status detectionAaron Rossetto2020-09-032-16/+38
| | | | | | | | | | | | | | | | This change improves the DPDK link status detection algorithm in the following ways: - The status of the links are checked at an interval of 250 ms. If all links report as being up, the driver proceeds. - If any of the DPDK links has not reported as being up by the end of the link status detection timeout (1000 ms by default), the algorithm throws a runtime error rather than proceeds with one or more down links. - Users may override the default link status detection timeout by passing dpdk_link_timeout=N, where N is the desired timeout in milliseconds, either via device arguments or in the UHD configuration file.
* docs: Add Windows-specific UHD Python module notesAaron Rossetto2020-09-031-0/+30
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* x300,mpmd: Increase recv frames for dpdk streamingSteven Koo2020-09-032-1/+16
| | | | | | | | With the default 32 frames, high rate DPDK streaming would overrun or drop samples. This defaults num_recv_frames to 512 for DPDK, which has shown to resolve these issues. Signed-off-by: Steven Koo <steven.koo@ni.com>
* docs: Add note about compiling on Ubuntu 20.04Aaron Rossetto2020-09-031-0/+31
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* rfnoc: replay: Add support for 32-bit memory address widthsettus2020-09-032-3/+3
| | | | | | Increases the supported memory sizes in software to 2^32 and beyond. Signed-off-by: mattprost <matt.prost@ni.com>
* mpm: Return 10 Gbs link speed on failuremattprost2020-09-011-0/+7
| | | | | | | | | | | The sysfs call used to determine link speed occasionally will fail and return -1. In order to mitigate side effects from this behavior, return 10 Gbs link speed instead of 1 Gbs. This mitigates problems that occur when this issue is seen on 10GbE ports. This approach was elected over returning -1 to be handled on the host side in order to avoid breaking mpm compatibility. Signed-off-by: ettus <matt.prost@ni.com>
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
| | | | | | | - Adds test coverage for stream command and status packets - Cleans up report output during simulation - Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can be run directly instead of just chdr_stream_endpoint_all_tb
* fpga: sim: Fix stream command and status modelsWade Fife2020-08-311-9/+9
| | | | | | | | This updates PkgChdrBfm to correct some errors when modeling stream command and stream status packets. - Fix behavior when CHDR_W = 512 - Fix assertions in read_ctrl()
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
| | | | | | This changes the behavior of the stream command with the INIT OpCode such that sending the command with 0 for the values causes no flow control stream status packets to be sent in response to incoming data.
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
| | | | | Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants.
* cmake: Use relative path to Python lib location for Windows installerAaron Rossetto2020-08-281-5/+17
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* rfnoc: enable SEPs with connect_through_blocksSteven Koo2020-08-281-2/+24
| | | | | | | | Calling on connect with SEPs in the path is not supported. This change enables connect_through_blocks to find SEPs in the connection chain and link the src and dest blocks directly. Signed-off-by: Steven Koo <steven.koo@ni.com>
* rfnoc: Exit disconnect() early if nodes not in node mapAaron Rossetto2020-08-281-0/+4
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* utils: b2xx_fx3_utils: Add unload-bootloadermichael-west2020-08-251-1/+32
| | | | | | | Added unload-bootloader option to cleanly unload a previously loaded bootloader image. It properly moves the VID, PID, and EEPROM data. Signed-off-by: michael-west <michael.west@ettus.com>
* firmware: b2xx: Update to newer Cypress FX3 SDKmichael-west2020-08-254-168/+130
| | | | | | | | | - Updated README with instructions on how to build using new SDK (1.3.4 as of this change) - Updated makefiles - Updated memory map patch Signed-off-by: michael-west <michael.west@ettus.com>
* B2xx: firmware: Fix address for serial numbermichael-west2020-08-251-1/+1
| | | | | | | | The address for the serial number was off by 2 bytes, causing a bad value in the USB descriptor. This only occurred if the bootloader image was loaded on the device. Signed-off-by: michael-west <michael.west@ettus.com>
* tests: fbs test: Fix issues around missing gitMartin Braun2020-08-252-3/+7
| | | | | | | | | - update_fbs.py would use git directly, instead of the requested git executable - There are other corner cases for the git executable detection, which are now all captured under a more general exception type Credit to Christopher Friedt for pointing out the original issue.
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2323-2679/+5
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* fpga: Update coding guidelinesWade Fife2020-08-201-30/+107
| | | | | | | | | | - Update recommended header - Update module examples - Add file/naming guidelines for modules - Add default_nettype recommendation - Add guidelines for generate statements - Recommend all caps for constants - Misc typos and adjustments
* Update CHANGELOGAaron Rossetto2020-08-191-0/+5
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* images: Update manifestAaron Rossetto2020-08-191-6/+6
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* mpm: exclude internal nic for network hostsSteven Koo2020-08-191-4/+35
| | | | | | | | | | Sometimes the internal nic address is routable in network mode. This causes mpm find to incorrectly set it as the addr. This commit removes the internal interfaces from the routable list. This also sets the forwarding interface as the last resort. mpm will prefer the SFP ports since they can be higher throughput. Signed-off-by: Steven Koo <steven.koo@ni.com>
* NI-2974: Add cal supportmichael-west2020-08-191-0/+1
| | | | Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
| | | | Add some missing CtrlPort signal widths to ctrlport.vh.
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
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* Prepare branch for 4.0.0.0-rc1 releaseAaron Rossetto2020-08-172-29/+225
| | | | | - Updated CHANGELOG - Updated manifest
* python: power cal: Minor fixes to power cal codeMartin Braun2020-08-172-5/+9
| | | | | | | | - Fix some typos - Fix incorrect arg name for RFSGPowerGenerator.enable() - Fix case where incorrect args would cause an uncaught TypeError. Now, if USRP is chose as signal generator, but fails to find one, a proper error is shown.
* uhd: Add APIs for getting the available power rangeMartin Braun2020-08-177-0/+99
| | | | | | | | | The previously added APIs for getting/setting power reference levels was missing an option to read back the currently available power levels (minimum and maximum power levels). This adds getters for TX and RX power ranges to multi_usrp and radio_control. The power API is thus now more similar to the gain API, which always had getters for gain ranges.
* X300: Adjusting 10GbE frame sizes for HW limitsmichael-west2020-08-171-2/+2
| | | | | | | Lowering X300 10GbE default frame sizes to max size supported by hardware. Signed-off-by: michael-west <michael.west@ettus.com>
* multi_usrp: Use multi_usrp::sptrs in graph disconnect lambdasAaron Rossetto2020-08-171-9/+12
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* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
| | | | | It was set to E320_HG, which is not a valid target, causing build errors unless -t E320_1G was provided to rfnoc_image_builder.
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
| | | | | Device was set to e31x, but this is not a valid device type. All e31x devices use the e310 device type.
* dpdk: clean up destruction order of dpdk context membersettus2020-08-141-4/+4
| | | | | | | Clear the io service map and the dpdk port map in the dpdk context destructor to force them to destruct before the dpdk context. Signed-off-by: ettus <matt.prost@ni.com>
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
| | | | | Thange allows the mux to switch cleanly between packets, if the mux select input is changed while a packet is in flight.
* README.md: Fix REDHAWK linkLane Kolbly2020-08-131-1/+1
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* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
| | | | | | | | The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags.
* rh: Enable inverse sinc filter for DAC37J82Martin Braun2020-08-121-1/+1
| | | | | This enables the inv_sinc_ab and inv_sinc_cd flags for the DAC, turning on the inverse sinc filter.
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
| | | | | | | This increases the size of the ingress buffers for the N320 radio to support 250MHz TX streaming rates. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
| | | | | | | | | This fixes some incorrectly handled clock crossings from axis_data_clk to axis_chdr_clk, which could have manifested as timing failures (on E320) or incorrect behavior, depending on the product and noc_shell configuration. Also cleans up trailing white space.
* rfnoc: set a nop destructor for clang crashSteven Koo2020-08-121-0/+5
| | | | | Clang will generate an illegal instruction if a virtual destructor isn't defined.
* rfnoc: Increase ctrlport_endpoint default timeoutSteven Koo2020-08-121-1/+1
| | | | The .1 second timeout fails on macOS. Expand this timeout to 1 second.
* uhd: Remove assignment to const var for mac buildSteven Koo2020-08-121-11/+0
| | | | | These values are already correctly set upstream and should not be modified since params is const.
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