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* rh: Phase DAC configuration clean-upHumberto Jimenez2018-10-301-6/+4
| | | | | | | | | | | | | | | | | | | | | - Confirmed the Phase DAC to be initialized at mid-scale. - Confirmed the Phase DAC step resolution for fine clock shifting. The clock synchronization algorithm relies on the Phase DAC to fine shift the sampling clocks on each daughterboard. Only a certain number of DAC codes are required for the actual clock adjustment, thus a different range of codes may be chosen by initializing the Phase DAC with a given value. With the selected range, one may measure the Phase DAC's linearity and step resolution, which defines how many steps are required when performing the fine shifting of the clocks. After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and 75%; it was found that the clock distribution PLL locks relatively faster when using mid-scale (2^15). By testing the Phase DAC's linearity, it was confirmed that the circuit resolution is 1.11 ps per code.
* rh: Deterministic latency optimization in JESD204BHumberto Jimenez2018-10-301-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Optimized JESD204B RX/TX links' latency. - Made JESD latency constant across supported frequencies. - Checking RX SYSREF capture in the FPGA deframer block. The JESD204B standard can be linked in such a way to produce a repeatable, deterministic delay from the framer to deframer. This is accomplished by setting up a LMFC (local multiframe clock) in both devices. The LMFCs are reset whenever a SYSREF edge is captured by the framer and deframer. Therefore, it is simple to control the LMFC rising edges in each device by implementing variable delay elements on the SYSREF pulses to the framer and deframer. Latency across the JESD204B TX/RX links should remain constant and deterministic across the supported sampling_clock_rate values. By testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with different delay values in the FPGA, one may decrease the latency and provide enough setup and hold margin for the data to be transfered through each JESD link. It was found that a different set of SYSREF delay values are required for sampling_clock_rate = 400 MSPS to match the latency of the other supported rates.
* debian: Update control files for .deb filesMartin Braun2018-10-294-21/+29
| | | | | | | | | - Better alignement with public Debian files. - Move to a different package name: libuhd003.so -> libuhd3.13.0.so This allows to install multiple packages in parallel for better ABI compatibility by third-party dependees. The new package replaces the old one. - Remove .shlibs file
* cmake: Change SOVERSION and VERSION for the library filesMartin Braun2018-10-292-2/+9
| | | | | | The SOVERSION will now match the ABI string, and the VERSION matches the full UHD version. This will allow easier parallel installation of multiple versions of UHD.
* cores:rx_frontend_core_3000: fix real modeGwenhael Goavec-Merou2018-10-291-0/+2
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* python: Add missing constructors of time_spec_tPiotr Krysik2018-10-251-0/+3
| | | | | | Currently Python interface of time_spec_t exposes only constructor with 'double' parameter. Other constructors are also important as they provide higher precision. This change adds them to the Python API.
* manifest: FPGA bug fixesBrent Stapleton2018-10-252-9/+11
| | | | | | | | | | | | | | Updating FPGA images for the following devices with the following bug fixes. No compat number bumps included in the changes. Also updating the submodule pointer. X3xx, N3xx, E3xx: - DDS flushing fix - Fix sequence number clearing B2xx: - Async reset from misc registers - Redistributed buffering in radio and xport
* rh: add support for rhodium devicesMark Meserve2018-10-2526-4/+6147
| | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ni.com>
* nijesdcore: add PRBS-31 testingMark Meserve2018-10-251-0/+37
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* nijesdcore: add eyescan utilityMark Meserve2018-10-253-4/+860
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* nijesdcore: add variable configuration supportMark Meserve2018-10-254-30/+50
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* mpm: tools: Added Rhodium ID to db-id utilityDerek Kozel2018-10-251-1/+3
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* Test: Add unit test for eeprom_utilsmichael-west2018-10-254-2/+63
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* X300: Prevent duplicate MAC and IP addresses from being programmed in MBMichael West2018-10-252-2/+104
| | | | EEPROM
* X300: Add recovery for duplicate IP addresses in EEPROMMichael West2018-10-252-19/+13
| | | | | - Limit initialization to ZPU communication if recover_mb_eeprom=1 is set in device args.
* mpm: e320: n3xx: Factor BIST code to common moduleMartin Braun2018-10-243-1070/+786
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* block_ctrl_base: add UHD_SAFE_CALL to destructorTrung Tran2018-10-241-13/+15
| | | | | This will stop the exception throw during destructor of E310 where new FPGA image(idle image) is load.
* n3xx: output exception string on boot init failureMark Meserve2018-10-241-1/+1
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* cmake: Bump CMake minimum version to 2.8.12Martin Braun2018-10-241-2/+2
| | | | | | This enables some interesting features we can now use in UHD, such as: - target_compile_options - add_compile_options
* UHD: Fix RX streamer SOB and EOB handlingMichael West2018-10-241-2/+9
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* mpm: Add lock_guard() functionMartin Braun2018-10-231-0/+22
| | | | | This allows sharing mutexes between C++ and Python, and uses the with statement to provide a locked-out context.
* multi_usrp: Improve documentation for set_{time,clock,sync}_sourceMartin Braun2018-10-221-14/+95
| | | | | - Added note on bad-value-handling (throws uhd::value_error) - Added notes on what happens on re-init
* docs: n3xx: Improve sections on clock/time referencesMartin Braun2018-10-221-9/+22
| | | | | | - Added more detail on how to use White Rabbit - Highlight the options with external clock source (with or without external time source)
* mpm:n3xx: improve set_time_source,set_clock_sourceTrung Tran2018-10-221-50/+88
| | | | | | Add coercing behavior to set_time_source and set_clock_source to a valid sync source. Also, skip set_sync_source if device already set to the corresponding one.
* mpm: i2c: Add vector-based transfer functionAlex Williams2018-10-193-0/+41
| | | | This could lead to a less-restricted implementation for use in Python.
* mpm: Add i2c APIs for simple transfersAlex Williams2018-10-1911-0/+496
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* mg: adding skip_rfic argumentTrung Tran2018-10-182-3/+6
| | | | | | This change to add skip_rfic as an device argument. skip_rfic should be only used in ref_clock bist tests to bring down the test time.
* e320_bist: print extra output ref_clock testsTrung Tran2018-10-181-3/+6
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* n3xx_bist: add ref_clock bistTrung Tran2018-10-181-45/+107
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* mpm: identify sysfs gpios more genericallyMark Meserve2018-10-184-22/+59
| | | | | - Allow generic path names to be given for each search parameter instead of only checking the label
* uhd: Add dual measurements to benchmark_streamerCiro Nishiguchi2018-10-181-113/+314
| | | | | Add options to run benchmark_streamer with multiple streamers running concurrently on separate threads.
* twinrx: revise adf5356 frac2 register calculationMark Meserve2018-10-171-1/+1
| | | | | - If FRAC2 isn't exactly FRAC1 at certain frequencies, drifting spurs can be seen in the spectrum
* B200: Restore asynchronous reset of AD936x.michael-west2018-10-174-8/+19
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* e320: Added E320 docs page, reg map updatedSugandha Gupta2018-10-172-0/+707
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* lmx2592: remove initial scratch register readbackMark Meserve2018-10-171-24/+0
| | | | | - This is the only read operation in the driver, so removing it simplifies the driver's requirements significantly.
* lmx2592: add spur dodgingMark Meserve2018-10-172-23/+330
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* lib: ad9361: De-boostify AD9361 driverMartin Braun2018-10-172-106/+195
| | | | No functional or API changes.
* N310: Clarify logging for when re-inits occurTrung Tran2018-10-161-0/+2
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* mpm: n3xx: Fix Pylint warningsMartin Braun2018-10-121-11/+12
| | | | | This commit contains whitespace and formatting changes only. No functional changes.
* mpm: dboard_manager: add more args to update_ref_clock_freqTrung Tran2018-10-123-8/+10
| | | | | | | | | | | | | | | Summary: This change will allow correct args to pass from mboard to dboards, that in turn can be useful for dboard manager. Details: In N310, the dboard manager needs the time source to be updated before calling update_ref_clock_source(), because it will trigger a reinit of the dboard, for which the time_source is essential to determine correct clock synchronizer settings. The special case is the white rabbit time source needs a different internal ref_clock_frequency for the clock synchronizer than the passed in ref_clock_freq.
* docs: Fix N210 MIMO Phase Alignment commandBrent Stapleton2018-10-121-1/+1
| | | | | | | The synchronization source for the N210 MIMO phase alignment needs to be set to anything other than 'pps' or 'auto' (which is actually 'pps'). 'default' skips the call to `set_time_unknown_pps`, which is the proper way to synchronize in this sitation.
* utils: fix bmark_rate MIMO synchronizationBrent Stapleton2018-10-121-9/+10
| | | | | | | | | | Fix USRP2 MIMO synchronization in benchmark_rate. When synchronizing N2XXs connected with a MIMO cable, only the master's time needs to be set; the slave will be synchronized automatically. Currently, calling set_time_unknown_pps will attempt to synchronize the slave on the next PPS, which can cause problems since the MIMO cable doesn't propogate a PPS signal.
* uhd: Improve documentation for the UHD exception typesMartin Braun2018-10-121-0/+51
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* multi_usrp: Add sync_source APIMartin Braun2018-10-112-6/+211
| | | | | | | | | | The sync_source API is an atomic setter for all sync-related settings. If supported by the underlying USRP, it can be faster to call set_sync_source() rather than sequentially calling set_clock_source() and set_time_source(). If the underlying device does not support the sync_source API, it will fall back to the set_clock_source() and set_time_source() APIs, making this change backward-compatiple.
* tools: Add tool to analyze settling time of gain of freq changesMartin Braun2018-10-111-0/+249
| | | | | | | | | | | | | | This tool uses the Python API to acquire a snapshot of samples during a gain or frequency change. It can be used to analyze the settling time of analog components, as well as the accuracy in time. It has two combinable ways of analyzing the data: 1) Write it to a file, or 2) plot the time-domain data. Example: This would receive several seconds of data from an X3x0 device, tune to 1 GHz, and then bump the gain by 30 dB after a set amount of time: $ rx_settling_time.py -a type=x300 -f 1e9 -g 0 --new-gain 30 --plot
* uhd: Add benchmark_streamer exampleCiro Nishiguchi2018-10-112-0/+498
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* uhd: Add traffic counter to null source sinkCiro Nishiguchi2018-10-112-0/+100
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* mpmd: Increase rpcc timeout when calling set_time_source()Trung Tran2018-10-111-0/+2
| | | | | | | set_time_source() for N310 and N300 can take longer than the default RPC client timeout of 2 seconds due to dboard initialization. We need increase this timeout, by using the init timeout value which is 2 minutes.
* docs: Added TwinRX pageDerek Kozel2018-10-095-0/+91
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* mpm: Add usrp_update_fsMartin Braun2018-10-092-0/+195
| | | | | | | This provides a new utility for MPM devices (usrp_update_fs.py), which goes through all the necessary steps to update a filesystem. Will trigger a mender update, but the tool is not specific to Mender and can be changed to use other methods in the future.
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