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* NI-2974: Add cal supportmichael-west2020-08-191-0/+1
| | | | Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
| | | | Add some missing CtrlPort signal widths to ctrlport.vh.
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
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* Prepare branch for 4.0.0.0-rc1 releaseAaron Rossetto2020-08-172-29/+225
| | | | | - Updated CHANGELOG - Updated manifest
* python: power cal: Minor fixes to power cal codeMartin Braun2020-08-172-5/+9
| | | | | | | | - Fix some typos - Fix incorrect arg name for RFSGPowerGenerator.enable() - Fix case where incorrect args would cause an uncaught TypeError. Now, if USRP is chose as signal generator, but fails to find one, a proper error is shown.
* uhd: Add APIs for getting the available power rangeMartin Braun2020-08-177-0/+99
| | | | | | | | | The previously added APIs for getting/setting power reference levels was missing an option to read back the currently available power levels (minimum and maximum power levels). This adds getters for TX and RX power ranges to multi_usrp and radio_control. The power API is thus now more similar to the gain API, which always had getters for gain ranges.
* X300: Adjusting 10GbE frame sizes for HW limitsmichael-west2020-08-171-2/+2
| | | | | | | Lowering X300 10GbE default frame sizes to max size supported by hardware. Signed-off-by: michael-west <michael.west@ettus.com>
* multi_usrp: Use multi_usrp::sptrs in graph disconnect lambdasAaron Rossetto2020-08-171-9/+12
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* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
| | | | | It was set to E320_HG, which is not a valid target, causing build errors unless -t E320_1G was provided to rfnoc_image_builder.
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
| | | | | Device was set to e31x, but this is not a valid device type. All e31x devices use the e310 device type.
* dpdk: clean up destruction order of dpdk context membersettus2020-08-141-4/+4
| | | | | | | Clear the io service map and the dpdk port map in the dpdk context destructor to force them to destruct before the dpdk context. Signed-off-by: ettus <matt.prost@ni.com>
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
| | | | | Thange allows the mux to switch cleanly between packets, if the mux select input is changed while a packet is in flight.
* README.md: Fix REDHAWK linkLane Kolbly2020-08-131-1/+1
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* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
| | | | | | | | The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags.
* rh: Enable inverse sinc filter for DAC37J82Martin Braun2020-08-121-1/+1
| | | | | This enables the inv_sinc_ab and inv_sinc_cd flags for the DAC, turning on the inverse sinc filter.
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
| | | | | | | This increases the size of the ingress buffers for the N320 radio to support 250MHz TX streaming rates. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
| | | | | | | | | This fixes some incorrectly handled clock crossings from axis_data_clk to axis_chdr_clk, which could have manifested as timing failures (on E320) or incorrect behavior, depending on the product and noc_shell configuration. Also cleans up trailing white space.
* rfnoc: set a nop destructor for clang crashSteven Koo2020-08-121-0/+5
| | | | | Clang will generate an illegal instruction if a virtual destructor isn't defined.
* rfnoc: Increase ctrlport_endpoint default timeoutSteven Koo2020-08-121-1/+1
| | | | The .1 second timeout fails on macOS. Expand this timeout to 1 second.
* uhd: Remove assignment to const var for mac buildSteven Koo2020-08-121-11/+0
| | | | | These values are already correctly set upstream and should not be modified since params is const.
* uhd: Disable optimizations for Mac for build speedSteven Koo2020-08-121-0/+9
| | | | | twinrx_gain_tables takes long time to build with optimizations on macOS / Clang. Turn them off for this platform.
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-112-3/+3
| | | | | | | | | | | | | The max FFT size was 4096, but we don't currently have any devices that can do that without modification. This is because, currently, the FFT size must be the same as the packet size, and the largest packet size supported by most devices is about 8000 bytes, or 2000 sc16 samples. Therefore, the largest FFT size supported without modifying other code is 1024 samples. This change frees up about 21% of the LUTs and 36% of the BRAM used by axi_fft and makes the software block controller and the IP agree on the maximum FFT size.
* examples: replay samples from filemattprost2020-08-113-414/+424
| | | | | | | This example exercises the Replay Block RFNoC API. The Replay records IQ data from a file and plays it back into a Radio for transmitting. Signed-off-by: mattprost <matt.prost@ni.com>
* rfnoc: Don't error when streamer isn't foundSteven Koo2020-08-111-8/+0
| | | | | | This commit resolves an issue where the disconnect call would fail if the streamer was created, but not connected. If disconnect gets called on a streamer that isn't on the graph, ignore it.
* rfnoc: Resolves streamer/link segfaults on pythonSteven Koo2020-08-114-24/+33
| | | | | | | | | This commit resolves a segfault that occurs during teardown. Since teardown isn't detereministic in python, there were cases where the graph would destruct before the streamers or links got chance to cleanup. This would result in a segfault. This change gives the lambda a shared pointer to the object the callback method is calling on, so that it won't destruct before being called.
* twinrx: update synthesizer register values for improved rf performancemattprost2020-08-112-14/+31
| | | | | | | | | | | | | Updated Register values for ADF5356: R2) Expand Frac2 to a 28-bit value for ADF5356 R6) Use negative bleed current for improved spurious performance R7) Set Fractional-N Lock Detect Precision to 12.0 ns because of bleed currents R8) Use magic number for reserved bits R9) Fix VCO Band Division calculation for ADF5356 RD) Expand Frac2 to a 28-bit value for ADF5356 Signed-off-by: mattprost <matt.prost@ni.com>
* python: Change default name for rfnoc_image_coreWade Fife2020-08-102-9/+16
| | | | | | | | This changes the default name of the image core file to <DEVICE>_rfnoc_image_core.v instead of naming it after the YAML file. This ensures that when you use a custom YAML file, the resulting FPGA build will use the generated rfnoc_image_core and static_router files, rather than just the generated static_router file.
* devtest: Support multi_usrp_test on WindowsSteven Koo2020-08-101-1/+6
| | | | | | Windows requires the command 'python' to prepend calls to .py files. This change moves the path to multi_usrp_test.py to an argument on Windows.
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
| | | | | This adds additional tests to the testbench to cover register reads and basic IFFT functionaltiy.
* X300: Update frame sizes for 10GbEmichael-west2020-08-071-7/+5
| | | | | | | | | Setting default frame sizes for 10 GbE to match an Ethernet MTU of 9000, which is recommended in the UHD manual for the X300. The MTU detection code is left untouched, so it will automatically adjust if the MTU is lower than 9000. Signed-off-by: michael-west <michael.west@ettus.com>
* Python API: Add bindings for disconnect APIsmichael-west2020-08-071-0/+7
| | | | | | | Add Python bindings for recently added rfnoc_graph::disconnect() methods. Signed-off-by: michael-west <michael.west@ettus.com>
* RFNoC: Revert change in streamer initializationmichael-west2020-08-072-2/+2
| | | | | | | Reverting inadvertent change in num_chans argument during tx/rx_streamer_impl construction. Signed-off-by: michael-west <michael.west@ettus.com>
* mpm: n3xx: Remove eth1, eth2 from interface listMartin Braun2020-08-071-8/+0
| | | | | | | | | These interfaces are renamed to sfp0 and sfp1 and thus don't exist. They were kept in MPM for a while after the rename, but that was many versions of UHD ago, and the current filesystem (which does the rename) is not compatible with older versions of UHD anyway (and vice versa). These aliases are thus dead code and can be removed.
* mpmd: Clean out link_if_mgrMartin Braun2020-08-072-7/+4
| | | | | | | | | The link_if_mgr used to be a factory for Liberio, UDP, and DPDK. Now, Liberio is gone and DPDK is handled by UDP. This makes the class superfluous. Instead of removing the class, we comment on this, and remove any DPDK references from the file.
* mpm: Remove SID classMartin Braun2020-08-074-76/+2
| | | | | | This class is a remnant of UHD 3, and is no longer used anywhere. SID is no longer used at all in UHD, in fact, which means the class did not represent a valid data structure.
* rfnoc: Remove M_PI usage to fix Windows buildsSteven Koo2020-08-074-15/+13
| | | | | | M_PI may not exist if _USE_MATH_DEFINES isn't defined before the first include of math.h or cmath on Windows. This changes avoids the issue all together by defining our own PI.
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
| | | | | | | | | | | | | This commit derives parameters for MAX10 devices if provided by the DEVICE parameter. MAX10 devices FIFO generator support up to 36 bit wide FIFOs using embedded memory (M9K) in simple dual port mode, which is treated equally to RAM in the parameters. In combination with sorting the ctrlport signals by usage, the used resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks for a ctrlport_clk_cross instance without time and portids.
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
| | | | | | | | | - Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions
* utils: Change template specialization namespacingBill Davis2020-08-051-8/+10
| | | | | There is a gcc bug for template specialization that causes compile errors. Reformatting the namespacing avoids the bug.
* tests: Add unit test for Keep One in N block controllerAaron Rossetto2020-08-052-0/+141
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* python: Add Keep One in N block controller bindingsAaron Rossetto2020-08-053-0/+34
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* rfnoc: Add Keep One in N block supportAaron Rossetto2020-08-055-0/+207
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* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-058-0/+1488
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* devtest: Update filter for e31x devicesSteven Koo2020-08-041-1/+1
| | | | Filter for e3x0 no longer matches e31x devices. Switch to e3xx.
* mpmd: Assume mgmt interface can route CHDR packetsSteven Koo2020-08-041-1/+15
| | | | | | | | | The e31x devices don't advertise CHDR interface availability when the low power FPGA is loaded. Since the e3xx and n3xx all route CHDR packets with Virtual NIC forwarding, it's safe to assume that if we can communicate with the mgmt_addr, we can communicate via CHDR too. We can then correctly set the reachability for the e31x from this assumption.
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