| Commit message (Collapse) | Author | Age | Files | Lines |
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Revert "cores: Update rx_frontend_gen3.v controls for 1/4-rate mixer"
Commit introduced 180 degree ambiguity in TwinRX phase alignment.
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The N value was getting written twice and the second value being
written was 1, which works for all use cases except when using
TwinRX. This change fixes several issues with TwinRX including
streaming failing to stop cleanly and incorrect decimation.
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- Update fpga-src submodule
- Update manifest
Signed-off-by: Michael West <michael.west@ettus.com>
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Removing the flush in configure_flow_control_out(). The flush is done
incorrectly because it just disables flow control and allows packets
to dump onto the crossbar, which could lock it up. It is also
incorrect to flush when connecting blocks. A connect should just
configure the SID and flow control and let any existing data flow to
the newly connected block. Flushing of a block should only be done
during creation or destruction of the block.
Signed-off-by: Michael West <michael.west@ettus.com>
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This reverts commit 655b9b0f8e8f8556d434404da51aaccd124bbc3a.
Signed-off-by: Michael West <michael.west@ettus.com>
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- modify PLL charge pump values to improve phase coherence
- affects reference clocks of 11.52 MHz, 23.04 MHz, and 30.72 MHz
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- ADC self test had magic numbers for default duration
- resource and addr can be no longer be both specified without a warning
- second_addr requires addr now, or you get a warning
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Before, it was only returning the master clock rate. Note: This function
is never used in UHD, this is merely for completion's sake.
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The addition of the constrained device args didn't account for those
rates, and thus, they were effectively unusuable ever since. This adds
those rates back as valid system ref rates.
This does not touch the actual clocking code in any way,
x300_clock_control has supported those rates for a while now.
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This makes more type-conversions explicit, to reduce the number of
warnings specifically for MSVC.
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This fixes a warning about multiple operators. Doesn't change any
functionality.
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Image name to be provided to bitbake command are named 'developer-image' and 'deployment-image'
i.e. with dash, not with underscore
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When using a buffer size smaller than recommended, a warning would be
printed with the wrong value (it would print the default value, not the
actual value).
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setuptools isn't compatible with Unix style path on Windows 10
machines. We need to convert any path before running setuptools.
Signed-off-by: Trung Tran <trung.tran@ettus.com>
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MP and bigobj should be at compile options level instead of
compile_flags(which are at target properties level).
We have been setting these options incorrectly. They are currently not
applied to any project.
Signed-off-by: Trung Tran <trung.tran@ettus.com>
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The function for setting up the RX frontend was erroneously looking at
previous TX settings to determine whether to submit a command. This
fixes the issue.
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A node is not a block, it doesn't use any block definition to
populate the number of input and output ports. This is equivalent to it
have undefined number of input and output ports.
The _find_child_node function relies on node input and output port size.
When port size is not defined we should not follow the active channel;
instead, we need to greedily to find all child node.
Without this change graph_search_test will fail.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
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The error message will now include the IP address of the client trying
to double-claim a device.
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Before, the log messages would occasionally print 6 digits worth of
precision for sample clock values that only require 2.
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MPM has a flag that identifies component reloads as requiring to restart
the RPC server. This change honours that flag, and doesn't cause a fatal
failure when reclaims fail to ack for certain operations.
For example, running uhd_image_loader on an N310 could fail after the
FPGA was reloaded because the communication to the RPC server was
temporarily interrupted. This is not always avoidable, since the RPC
server does actually go down, and Ethernet connections might also be
lost. So, we cut our losses and accept failures in that case.
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- UHD's calibration utilities use the LO frequency, so this is the
frequency we should be using too.
- Disables loaded corrections in lowband, as the utilities will not
generate valid corrections at these frequencies. Manual corrections
can still be added via the property tree.
- Changed corrections logging to include frequency and less certainty
of the correction file's existence.
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- Fixes a bug where a previous setting could carry over between
sessions.
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- The other cal utilities (TX IQ and TX DC) already do this.
- This fixes calibration for certain frequencies on N320/N321.
- Old calibration data is still valid after this change.
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The N320 has FPGA types (XQ, AQ) which cannot be derived from the mboard
regs in the same way as the non-QSFP variants. We therefore bite the
bullet and hardcode those.
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The QSFP board can't be detected if support for it is not baked into
the current FPGA image, so the warning on its absence may be incorrect.
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Update filesystems, SDKs, and mender artifacts for N3xx, E320 to
v3.14.0.0-rc2.
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Fixup for last commit (9105f4fe) to update FPGA submodule.
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This fixes an issue where the git hash was not properly encoded in the
FPGA image.
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When running
$ n3xx_bist ddr3
The test will now load the AA image if the BIST fails, unless the user
specifies
$ n3xx_bist ddr3 -o skip_load_fpga=1
The rationale is that by default, the AA image is the only one that
includes the DmaFIFO block.
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The capability to run the DDR3 BIST is built into the DmaFIFO RFNoC
block, which is not always available. This change performs a quick check
before for its existence before retrieving the throughput values, and
thus can provide a better error message in that case.
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We can't guarantee that there is actually a DDR3/DRAM FIFO block on the
image. So, don't run that test by default.
In order to run the DDR3 bist, running `n3xx_bist ddr3` is still valid.
However, it requires an image with the DRAM FIFO enabled.
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Fixes uhd_usrp_probe FPGA version githash to report the
correct hash and not 'UNKNOWN'.
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Update N320 CPLD and N300/N310 AA images.
Signed-off-by: Michael West <michael.west@ettus.com>
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The previous zip file had accidentally archived the wrong images. This
provides the correct images. From uhd_usrp_probe:
- FPGA Version: 5.3
- FPGA git hash: 4bc2c6f.clean
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Without this patch, the N320 code will rely on an error to occur to
determine the non-existence of the N321 LO distribution board. While
this works, it forces an error message where there's no error. This will
first check for the existence of the board before trying to initialize
it.
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Remove "${prefix}/lib" from the DYLD path for APPLE only. Apple's DYLD
uses the paths embedded in the binary file (library or executable) as a
secondary means for finding referenced libraries. Explicitly including
"${prefix}/lib" can result in libraries being found and used by System
frameworks that are not compatible with them. Moving to just using build
paths fixes this issue.
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Hardware revision was increased due to new firmware. No software
changes are required.
Signed-off-by: michael-west <michael.west@ettus.com>
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The configure_flow_control_out function was set to dump any packets
onto the crossbar, which could cause issues on the crossbar and in
downstream blocks. Replacing wil a call to the _flush() function in
the block_ctrl_base parent class, which drops the packets so they do
not get put onto the crossbar.
Signed-off-by: Michael West <michael.west@ettus.com>
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FC ACK packets are unnecessary on lossless links and degrade overall
performance. This change disables those packets on all lossless links.
Signed-off-by: Michael West <michael.west@ettus.com>
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The RFNoC call set_rx_gain() would previously ignore the additional 6 dB
that can be set on the ADC. On the BasicRX board in particular, this
meant there was no RX gain setting at all.
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