| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: michael-west <michael.west@ettus.com>
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- Updated CHANGELOG
- Updated fpga-src submodule
- Updated version
- Updated manifest for images
Signed-off-by: Michael West <michael.west@ettus.com>
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Signed-off-by: Matthew Crymble <matthew.crymble@ni.com>
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Newer revisions of the E320 and N3xx motherboards use EEPROM version 3,
and store a rev_compat field. The rev_compat is the last revision that
this hardware is compatible with. We now use that instead of simply the
revision.
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This includes a rev_compat field, which we can use to identify the last
hardware revision this hardware is compatible with. Example: Say the
current hardware revision is 7, but it is compatible with version 5,
then we store 7 as the current rev, and 5 as the rev_compat. Software
can now check the rev_compat rather than the current rev for
compatibility. This makes MPM more future-proof against minor,
compatible hardware changes.
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The tick_node was trying to find the current tick rate by only querying
active blocks (i.e., blocks that were flagged active-streaming).
However, this is not necessary since we require all blocks to run at the
same tick rate.
In theory, querying active-only ports should be fine, but due to some
idiosyncrasies in our current graph code, connecting a single streamer
to channel 1 (out of 0, 1) would try and get the info from the wrong
port. This is not a fix to the graph code, but the change to tick_node
is also appropriate and is sufficient to fix the "late packets on
channel 1" issue.
This issue would manifest when sending timed packats to channel 1 in
a single-channel streamer. The problem is that it wouldn't be able to
read the correct tick rate.
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The colour codes used for console logging were incorrectly defined.
Some colours would simply not rendered this way (e.g., red), others
had the boldness flag wrong.
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- adds a new mode to the adf435x driver which provides general spur performance
improvements
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- No driver changes required
Signed-off-by: michael-west <michael.west@ettus.com>
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This will clear the property tree, block registry, transport managers,
and motherboard list on destruction of mpmd_impl.
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This will make sure that the context holder for the liberio context is
destroyed when the last liberio transport is destroyed, and not on
termination of the program.
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The reclaim task loop is asnychronous to the main thread which can
result in spurious reclaim call to the device after unclaim has been
called. This is especially risky if the device has already entered a
non-serviceable state after unclaim e.g. idle state.
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
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We need to properly contraint the send/recv_frame_size based on the
minimum MTU of all the down/upstream blocks. This fixes the issue with
E310 tx/rx streaming as it has smaller MTU sizes than the other usrps.
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This fixes a potential mismatch between the returned frequency and
clock rate and the actual value. The new function get_clock_rate is
need for async call to set_clock_rate in E3xx devices
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- In general, some comments to clarify the dependencies installation and building process for windows users.
- Add a comment to the required packages for MSCV.
- Provide instructions to install Python requirements.
- Add the instructions of NSIS installation.
- Add comments to the version match between different installers.
- Clarify the instructions of building process using Cmake
- Add a subsection to show how a binary UHD installer can be obtained.
- Correct the URL of Doxygen.
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In log.cpp, a deadlock can occur while popping elements from the log
queue. If the queue is empty, the call does not timeout, and waits
infinitely. Replacing pop_with_wait() with pop_with_timed_wait() solves
this issue.
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- Update MB EEPROM
- Add bootloader load command to fx3 util
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- Adds custom bootloader code
- Refactor common functions in firmware and bootloader
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dpdk_zero_copy.hpp was referenced in multiple places using relative
paths. Let's throw it in uhdlib for easy access.
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Use dpdk_simple together with a control transport factory.
Where udp_zero_copy is used, use dpdk_zero_copy if use_dpdk=1.
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With the same APIs, this will make it easier to add support for X310.
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The NI-2974 has a X310 inside but reports a different "product" when
polled. This prevents the image_loader from flashing a new FPGA image,
this patch enables this.
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Occasionally, MPM would check its links before the kernel would report
link up, and it would then shave those ports off the CHDR link list
prematurely. This commit adds a second of wait to allow the kernel time
to respond.
It also includes some additional reporting of link status, since Intel
PMDs may report a misleading initial state upon bring-up.
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This reverts commit c8e01d4bd5bef30ef6e6080c60bc8b4706eb1200.
The commit introduced random phase offsets for TwinRX phase alignment.
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Revert "cores: Update rx_frontend_gen3.v controls for 1/4-rate mixer"
Commit introduced 180 degree ambiguity in TwinRX phase alignment.
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The N value was getting written twice and the second value being
written was 1, which works for all use cases except when using
TwinRX. This change fixes several issues with TwinRX including
streaming failing to stop cleanly and incorrect decimation.
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- Update fpga-src submodule
- Update manifest
Signed-off-by: Michael West <michael.west@ettus.com>
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Removing the flush in configure_flow_control_out(). The flush is done
incorrectly because it just disables flow control and allows packets
to dump onto the crossbar, which could lock it up. It is also
incorrect to flush when connecting blocks. A connect should just
configure the SID and flow control and let any existing data flow to
the newly connected block. Flushing of a block should only be done
during creation or destruction of the block.
Signed-off-by: Michael West <michael.west@ettus.com>
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This reverts commit 655b9b0f8e8f8556d434404da51aaccd124bbc3a.
Signed-off-by: Michael West <michael.west@ettus.com>
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- modify PLL charge pump values to improve phase coherence
- affects reference clocks of 11.52 MHz, 23.04 MHz, and 30.72 MHz
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- ADC self test had magic numbers for default duration
- resource and addr can be no longer be both specified without a warning
- second_addr requires addr now, or you get a warning
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Before, it was only returning the master clock rate. Note: This function
is never used in UHD, this is merely for completion's sake.
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The addition of the constrained device args didn't account for those
rates, and thus, they were effectively unusuable ever since. This adds
those rates back as valid system ref rates.
This does not touch the actual clocking code in any way,
x300_clock_control has supported those rates for a while now.
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This makes more type-conversions explicit, to reduce the number of
warnings specifically for MSVC.
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