| Commit message (Collapse) | Author | Age | Files | Lines |
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If platform.system() is 'Windows', the Python script will stall on
error before terminating, e.g., when an import is missing or when an
unexpected Exception occurred during the execution.
The rationale is that many Windows users run this script directly,
without a shell, and wouldn't have a way to see error messages from the
script in that case.
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Since the uhd_images_downloader is so tightly integrated into our
infrastructure, we've dropped support for .tar.gz and .tar.xz file for
this particular purpose. Note that UHD releases still receive images in
all three formats.
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No functional changes. The main effort was to reduce the length of
main() and reduce the number of Pylint warnings.
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Note: All archives shipped using this tool are zip files. However, this
allows us to ship other types of files, which will be downloaded and
sorted into the images directory as-is.
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This download limit prevents users from accidentally downloading really
large files. The default limit is 100 MiB. When a file is selected for
download that exceeds this size, the user is prompted if she really
wants to download that file.
By specifying --yes (or -y), this can can be bypassed. Example:
$ uhd_images_downloader --yes -t sdimg
Will match all files that match 'sdimg', which are typically larger than
100 MiB, without interaction.
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This will answer 'yes' to all questions that are asked and allows to
script the downloader. Example:
$ uhd_images_downloader -t sdimg -y
Any interaction that the script will have with the user will be skipped.
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Running
$ uhd_images_downloader -l
will now print the full URL of the target. By specifying
$ uhd_images_downloader -l --url-only
It will *only* print the URLs, nothing else, making this suitable for
scripting. The list will always go to stdout, whereas the logging is
going to stderr and thus can easily be siphoned off.
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This makes it easier to detect errors in derived classes that expect
getters in radio_ctrl_impl to also do error checking.
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This will release the i2c device when it's not in use. If MPM hangs on
to the i2c devices, we won't be able to cleanly change FPGA images--The
kernel hangs up the process until the refcount drops to zero.
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Adding clang-format configuration file. The chosen style is meant to
match current UHD coding style, except in certain cases where we have
consciously decided to format our code in a particular way.
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This function grabs the i2c character device path from the OF_NAME
property. That property must be unique in the device tree!
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None of our FPGA images support a 120 MHz master clock rate, so the UHD
code should match that.
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This enables a default package for Rhodium images.
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- Improves performance for frequencies greater than 3.5 GHz
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- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
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This makes the noc traffic counter register actually reflect the
registers in the FPGA. The FPGA register names were changed prior to
merging to master, and the ready count registers were removed.
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- Improves spur performance
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- Confirmed the Phase DAC to be initialized at mid-scale.
- Confirmed the Phase DAC step resolution for fine clock shifting.
The clock synchronization algorithm relies on the Phase DAC to fine
shift the sampling clocks on each daughterboard.
Only a certain number of DAC codes are required for the actual clock
adjustment, thus a different range of codes may be chosen by
initializing the Phase DAC with a given value. With the selected range,
one may measure the Phase DAC's linearity and step resolution, which
defines how many steps are required when performing the fine shifting
of the clocks.
After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and
75%; it was found that the clock distribution PLL locks relatively
faster when using mid-scale (2^15). By testing the Phase DAC's
linearity, it was confirmed that the circuit resolution is 1.11 ps per
code.
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- Optimized JESD204B RX/TX links' latency.
- Made JESD latency constant across supported frequencies.
- Checking RX SYSREF capture in the FPGA deframer block.
The JESD204B standard can be linked in such a way to produce a
repeatable, deterministic delay from the framer to deframer. This is
accomplished by setting up a LMFC (local multiframe clock) in both
devices.
The LMFCs are reset whenever a SYSREF edge is captured by the framer
and deframer. Therefore, it is simple to control the LMFC rising edges
in each device by implementing variable delay elements on the SYSREF
pulses to the framer and deframer.
Latency across the JESD204B TX/RX links should remain constant and
deterministic across the supported sampling_clock_rate values. By
testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with
different delay values in the FPGA, one may decrease the latency and
provide enough setup and hold margin for the data to be transfered
through each JESD link.
It was found that a different set of SYSREF delay values are required
for sampling_clock_rate = 400 MSPS to match the latency of the other
supported rates.
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- Better alignement with public Debian files.
- Move to a different package name: libuhd003.so -> libuhd3.13.0.so
This allows to install multiple packages in parallel for better ABI
compatibility by third-party dependees. The new package replaces the
old one.
- Remove .shlibs file
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The SOVERSION will now match the ABI string, and the VERSION matches the
full UHD version. This will allow easier parallel installation of
multiple versions of UHD.
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Currently Python interface of time_spec_t exposes only constructor with
'double' parameter. Other constructors are also important as they
provide higher precision. This change adds them to the Python API.
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Updating FPGA images for the following devices with the following bug
fixes. No compat number bumps included in the changes. Also updating
the submodule pointer.
X3xx, N3xx, E3xx:
- DDS flushing fix
- Fix sequence number clearing
B2xx:
- Async reset from misc registers
- Redistributed buffering in radio and xport
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Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ni.com>
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EEPROM
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- Limit initialization to ZPU communication if recover_mb_eeprom=1 is
set in device args.
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This will stop the exception throw during destructor of E310 where
new FPGA image(idle image) is load.
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This enables some interesting features we can now use in UHD, such as:
- target_compile_options
- add_compile_options
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