aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Merge branch 'fpga_master'Josh Blum2012-03-129-13/+16
|\
| * fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
* | usrp: fix wildcard set for time/clock sourceJosh Blum2012-03-121-2/+2
* | uhd: added fullscale option stream argJosh Blum2012-03-113-1/+10
* | Make DBSRX* set default bandwidth based on codec rateJason Abele2012-03-112-2/+7
* | Fix RSSI measurementJason Abele2012-03-113-19/+4
* | Merge branch 'fpga_master'Josh Blum2012-03-114-101/+3
|\|
| * fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
* | usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
* | Changes Windows installer filename to match naming convention of Ubuntu and F...Nicholas Corgan2012-02-291-0/+1
* | uhd: fix sc16 to sc8 conversion tableJosh Blum2012-02-291-12/+12
* | usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
* | Changing UHD to 'USRP HD' in one last place.Ben Hilburn2012-02-281-1/+1
* | usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
* | Changes images CMakeLists.txt to be consistent with new UHD version naming sy...Nicholas Corgan2012-02-281-6/+5
* | uhd: fixed some compile warnings for msvcJosh Blum2012-02-284-5/+5
* | cmake:Nicholas Corgan2012-02-284-14/+17
* | uhd: fixed send pkt handler, vrt packet type was uninitializedJosh Blum2012-02-271-0/+1
* | usrp2: removed unused memory map entriesJosh Blum2012-02-271-5/+1
* | usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
* | usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
* | Try really hard to get cmake to use compiler flags from the toolchain file.Philip Balister2012-02-211-2/+2
* | usb: added /opt/local to libusb search pathJosh Blum2012-02-211-1/+2
* | usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
* | usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
* | usrp2: changed download url for dd.exeJosh Blum2012-02-182-2/+2
* | Merge branch 'fpga_master'Josh Blum2012-02-183-4/+26
|\|
| * usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| * vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
* | uhd: added -fvisibility-inlines-hiddenJosh Blum2012-02-181-1/+2
* | Merge branch 'next'Josh Blum2012-02-17123-1729/+3954
|\ \
| * | Merge branch 'fpga_next' into nextJosh Blum2012-02-1754-1070/+2565
| |\|
| | * dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
| | * dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
| | * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
| | * dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | * dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | * dsp rework: pass enables into glue, update power trig, parameterize, fix modu...Josh Blum2012-02-109-103/+145
| | * dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
| | * B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
| | * dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
| | * b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
| | * b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
| | * power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
| | * dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0226-262/+544
| | * power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
| | * dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
| | * dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
| | * dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
| | * Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
| | |\
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 19:39:53 +0000