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* Merge branch 'fpga_next' into nextJosh Blum2012-04-104-3/+63
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| * Merge branch 'master' into nextJosh Blum2012-04-095-7/+67
| |\ | | | | | | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v
| | * Merge branch 'maint'Josh Blum2012-04-095-6/+6
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| | | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-095-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
| | * | Merge branch 'maint'Josh Blum2012-04-022-5/+5
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| | * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
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| * | | Merge branch 'master' into nextJosh Blum2012-03-264-85/+92
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* | | | Merge branch 'master' into nextJosh Blum2012-04-0328-357/+722
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: host/examples/CMakeLists.txt
| * \ \ \ Merge branch 'maint'Josh Blum2012-04-033-8/+8
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| | * \ \ \ Merge branch 'fpga_maint' into maintJosh Blum2012-04-022-5/+5
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| | | * | | b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-012-5/+5
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change.
| | * | | examples: fix bsd compilation for network relay exampleJosh Blum2012-04-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes compilation on platforms that dont have one of the OS defines by providing #else case for rx_dsp_buff_size constant. This also makes OSX the special case and assumes other OS can handle the large RX socket buffer size.
| * | | | Merge branch 'docs_stuff'Josh Blum2012-03-3016-343/+349
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| | * | | | docs: All instances of "the UHD" have been changed to "UHD". All paths, ↵Nicholas Corgan2012-03-3013-146/+145
| | | | | | | | | | | | | | | | | | | | | | | | filenames, variables, etc. have been uniformly emphasized.
| | * | | | docs: Format consistency, such as representation of program names or filepathsNicholas Corgan2012-03-2912-131/+136
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| | * | | | docs: Adding links to specific installation instructions for Windows and ↵Nicholas Corgan2012-03-297-81/+83
| | | | | | | | | | | | | | | | | | | | | | | | Linux, as well as general formatting consistency/clean-up
| * | | | | uhd: windows fixes and formatting for hammer exampleJosh Blum2012-03-301-293/+293
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| * | | | | Merge branch 'maint'Josh Blum2012-03-297-5/+15
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| | * | | | usrp1: stop threads in deconstructorJosh Blum2012-03-293-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its important to stop the threads before we let the other smart point objects naturally deconstruct to avoid thread-based race conditions. The attempt to deconstruct the tree and soft time ctrl had a bug because the tree had references in subtrees within the dboard manager class. Rather than continue to fix this method and deconstruct the tree to free up soft time ctrl, it seems simpler to just stop the thread in soft time ctrl, and then let it naturally deconstruct later by ref count.
| | * | | | cmake: Binaries give notification before installing or uninstalling UHD. ↵Nicholas Corgan2012-03-294-1/+5
| | |/ / / | | | | | | | | | | | | | | | Better to give an output than just an empty pause.
| * | | | examples: Transport Hammer - a stress test that calls for random or ↵Nicholas Corgan2012-03-272-0/+349
| | | | | | | | | | | | | | | | | | | | user-specified amounts of TX or RX samples with little to no delay between calls
* | | | | Merge branch 'master' into nextJosh Blum2012-03-268-126/+169
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| * | | | Merge branch 'maint'Josh Blum2012-03-262-4/+25
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| | * | | dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHzJosh Blum2012-03-261-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This fixes the lockup/clocking condition when the following hw combo is used: USRP1 r4.5 + DBSRX + another i2c board
| | * | | usrp2: possible fix for invalid broadcast repliesJosh Blum2012-03-261-3/+17
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| * | | | Merge branch 'maint'Josh Blum2012-03-264-85/+92
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| | * | | Merge branch 'fpga_maint' into maintJosh Blum2012-03-264-85/+92
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| | | * | B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
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| | | * | fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
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| | | * | b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
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| | | * | b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
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| | | * | b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
| * | | | fx2: simplify i2c code and overload eeprom read/writeJosh Blum2012-03-261-15/+24
| | | | | | | | | | | | | | | | | | | | | | | | | Overload eeprom routines to do it in 1 transaction, since default will split it up into many for each byte.
| * | | | Merge branch 'maint'Josh Blum2012-03-261-22/+28
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| | * | | uhd: use release mode and git count for stable and unstable buildsJosh Blum2012-03-261-22/+28
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* | | | | Merge branch 'master' into nextJosh Blum2012-03-231-1/+1
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| * | | | Merge branch 'maint'Josh Blum2012-03-231-1/+1
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| | * | | Changes preinst.in to 'echo' instead of 'ls'Nicholas Corgan2012-03-231-1/+1
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* | | | | uhd: updated sync docs for timed commandsJosh Blum2012-03-231-1/+34
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* | | | | Merge branch 'fpga_next' into nextJosh Blum2012-03-2312-426/+1454
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| * | | | spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
| * | | | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
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| * | | | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
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| * | | | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
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| * | | | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
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| * | | | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
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| * | | | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
| * | | | spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
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| * | | | fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
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| * | | | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-163-92/+122
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